u-boot.git/drivers/pci, branch v2021.04

pci: layerscape: Change to allocate zeroed memery for struct ls_pcie

2021-03-23T12:36:07Z

As on some incipient Layerscape platforms (LS1043A series) there isn't separate PF control register block, these registers reside in the LUT register block, so when the driver detected there isn't 'ctrl', it will assign the 'lut' address to the ls_pcie->ctrl. The current code allocate memory for the struct ls_pcie with random contents, this can result in skipping to assign the ls_pcie->ctrl with the 'lut' address, then further crash with the incorrect address. Fixes: 118e58e26eba ("pci: layerscape: Split the EP and RC driver") Signed-off-by: Hou Zhiqiang Reviewed-by: Vladimir Oltean Reviewed-by: Priyanka Jain

arm: a37xx: pci: Implement workaround for the readback value of VEND_ID

2021-03-12T06:44:21Z

Marvell Armada 3720 Functional Errata, Guidelines, and Restrictions document describes in erratum 4.1 PCIe value of vendor ID (Ref #: 243): The readback value of VEND_ID (RD0070000h [15:0]) is 1B4Bh, while it should read 11ABh. The firmware can write the correct value, 11ABh, through VEND_ID (RD0076044h [15:0]). Implement this workaround in U-Boot PCIe controller driver aardvark for both PCI vendor id and PCI subsystem vendor id. This change affects PCI vendor id of PCIe root bridge emulated by Linux kernel. With this change Linux kernel reports correct vendor id 11AB. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese

pci: mpc85xx: Support 64-bit bus and cpu address

2021-03-05T04:55:43Z

At present the driver only supports 32-bit bus and cpu address. The controller's outbound registers/fields for extended address are not programmed. Let's program them to support 64-bit bus and cpu address. Signed-off-by: Bin Meng Reviewed-by: Heiko Schocher Reviewed-by: Priyanka Jain

pci: mpc85xx: Support controller register physical address beyond 32-bit

2021-03-05T04:55:43Z

devfdt_get_addr_index() returns fdt_addr_t which might be a 64-bit physical address. Use map_physmem() to return the virtual address that can be used by a 32-bit machine. Signed-off-by: Bin Meng Reviewed-by: Heiko Schocher Reviewed-by: Priyanka Jain

pci: mpc85xx: Wrap LAW programming with CONFIG_FSL_LAW

2021-03-05T04:55:43Z

For the QEMU ppce500 machine, LAW registers are not implemented hence CONFIG_FSL_LAW is not turned on and all LAW APIs are not available. We should wrap all LAW registers programming in the mpc85xx PCI driver with CONFIG_FSL_LAW. Signed-off-by: Bin Meng Reviewed-by: Heiko Schocher Reviewed-by: Priyanka Jain

pci: fsl_pci_init: Dynamically allocate the PCI regions

2021-03-05T04:55:42Z

Commit e002474158d1 ("pci: pci-uclass: Dynamically allocate the PCI regions") changes 'struct pci_controller'.regions from pre-allocated array of regions to dynamically allocated, which unfortunately broken lots of boards that still use the non-DM PCI driver. This patch changes the non-DM fsl_pci_init driver to dynamically allocate the regions, just like what's done in the pci uclass driver. Fixes: e002474158d1 ("pci: pci-uclass: Dynamically allocate the PCI regions") Signed-off-by: Bin Meng Reviewed-by: Simon Glass Reviewed-by: Priyanka Jain

pci: pci_mvebu: set local dev to number 1

2021-02-26T09:22:29Z

Linux displays the real PCIe card connected to a mvebu PCIe slot as device 0, not 1. This is done by setting local dev number to 1, so that the local "Marvell Memory controller" device is on address 1. Let's do it also in U-Boot. With this commit the pci command in U-Boot prints something like: => pci Scanning PCI devices on bus 0 BusDevFun VendorId DeviceId Device Class Sub-Class _____________________________________________________________ 00.00.00 0x168c 0x003c Network controller 0x80 Signed-off-by: Marek Behún Cc: Stefan Roese Cc: Phil Sutter Cc: Mario Six Cc: Baruch Siach Reviewed-by: Stefan Roese

pci: pci_mvebu: refactor validation of addresses for config access

2021-02-26T09:22:29Z

Refactor validation of bdf parameter in mvebu_pcie_read/write_config functions. We can simplify the code by putting the validation into separate function. Also there are always only two devices visible on local bus: * on slot configured by function mvebu_pcie_set_local_dev_nr() (by default this register is set to 0) there is a "Marvell Memory controller", which isn't useful in root complex mode, * on all other slots the real PCIe card connected to the PCIe slot. We can simplify the code even more by simply allowing access only to the real PCIe card. Signed-off-by: Marek Behún Cc: Stefan Roese Cc: Phil Sutter Cc: Mario Six Cc: Baruch Siach Reviewed-by: Stefan Roese

pci: pci_mvebu: debug rd/wr config as other drivers do

2021-02-26T09:22:29Z

Other drivers (aardvark, intel_fpga) print "(addr,size,val)" when debugging is enabled. Print size for pci_mvebu as well. Signed-off-by: Marek Behún Cc: Stefan Roese Cc: Phil Sutter Cc: Mario Six Cc: Baruch Siach Reviewed-by: Stefan Roese

pci: pci_mvebu: cosmetic fix

2021-02-26T09:22:29Z

Write bdf address in a same way in mvebu_pcie_read/write_config. Signed-off-by: Marek Behún Cc: Stefan Roese Cc: Phil Sutter Cc: Mario Six Cc: Baruch Siach Reviewed-by: Stefan Roese