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<title>u-boot.git/drivers/pci, branch v2021.10</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/pci?h=v2021.10</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/pci?h=v2021.10'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2021-09-13T22:23:13Z</updated>
<entry>
<title>pci: Drop DM_PCI</title>
<updated>2021-09-13T22:23:13Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2021-08-02T00:54:44Z</published>
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<id>urn:sha1:3232bdf0b30b057ace64f192bc55a0bed4199770</id>
<content type='text'>
This option has not effect now. Drop it, using PCI instead where needed.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>pci: Drop PCI_INDIRECT_BRIDGE</title>
<updated>2021-09-13T22:23:13Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2021-08-02T00:54:43Z</published>
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<id>urn:sha1:23cacd57040244e3ecab3e95a36f08c8242159b2</id>
<content type='text'>
This does not work with driver model so can be removed.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>arm: a37xx: pci: Don't spam about PIO Response Status</title>
<updated>2021-09-10T07:01:51Z</updated>
<author>
<name>Marek Behún</name>
<email>marek.behun@nic.cz</email>
</author>
<published>2021-09-07T15:27:08Z</published>
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<id>urn:sha1:157bc52b0fa9d75611aeca9668c5227d6e64e05e</id>
<content type='text'>
Use dev_dbg() instead of dev_err() in pcie_advk_check_pio_status().

For example CRS is not an error status, it just says that the request
should be retried.

Without this, U-Boot spams the terminal with
  pcie_advk pcie@d0070000: Non-posted PIO Response Status: UR, 0xc80 @ 0x100000
  pcie_advk pcie@d0070000: Non-posted PIO Response Status: UR, 0xc80 @ 0x108000
  pcie_advk pcie@d0070000: Non-posted PIO Response Status: UR, 0xc80 @ 0x110000
  pcie_advk pcie@d0070000: Non-posted PIO Response Status: UR, 0xc80 @ 0x120000
  pcie_advk pcie@d0070000: Non-posted PIO Response Status: UR, 0xc80 @ 0x128000
  pcie_advk pcie@d0070000: Non-posted PIO Response Status: UR, 0xc80 @ 0x130000
  ...
when a device is not connected to a PCIe switch (Unsupported Request
from the switch).

Signed-off-by: Marek Behún &lt;marek.behun@nic.cz&gt;
Reviewed-by: Pali Rohár &lt;pali@kernel.org&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>arm: a37xx: pci: Implement re-issuing config requests on CRS response</title>
<updated>2021-09-10T07:01:51Z</updated>
<author>
<name>Pali Rohár</name>
<email>pali@kernel.org</email>
</author>
<published>2021-08-27T12:14:44Z</published>
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<id>urn:sha1:d9ac6e28afae08f4d0c2116db4279fa59ea7c838</id>
<content type='text'>
According to PCIe base specification, if CRS Software Visibility is not
enabled, the Root Complex must re-issue the Configuration Request as a new
Request.

Normally this part of Root Complex is implemented in hardware but aardvark
is somehow special and does not implement it in hardware and expect that
handling of config requests are fully implemented in software.

This re-issuing functionality is required also because U-Boot does not
support CRS Software Visibility feature and therefore expects that Root
Complex re-issues requests as is specified in PCIe base specification.

Retry / re-issue config request up to the PIO_MAX_RETRIES, to prevent
infinite loop. After retry count exceed PIO_MAX_RETRIES, returns failure.

Signed-off-by: Pali Rohár &lt;pali@kernel.org&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>arm: a37xx: pci: Disable returning CRS response</title>
<updated>2021-09-10T07:01:51Z</updated>
<author>
<name>Pali Rohár</name>
<email>pali@kernel.org</email>
</author>
<published>2021-08-27T12:14:43Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=758262bc266aa65cfbfd74033c3ac1e4e67c92ec'/>
<id>urn:sha1:758262bc266aa65cfbfd74033c3ac1e4e67c92ec</id>
<content type='text'>
There was mistake in commit 4cd61c43fd51 ("arm: a37xx: pci: Fix handling
PIO config error responses"). U-Boot does not support handling of CRS
return value for PCI_VENDOR_ID config read request and also does not set
CRSSVE bit.

Therefore disable returning CRS response for now.

Signed-off-by: Pali Rohár &lt;pali@kernel.org&gt;
Fixes: 4cd61c43fd51 ("arm: a37xx: pci: Fix handling PIO config error responses")
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>arm: a37xx: pci: Fix handling PIO config error responses</title>
<updated>2021-08-11T06:42:26Z</updated>
<author>
<name>Pali Rohár</name>
<email>pali@kernel.org</email>
</author>
<published>2021-08-09T07:53:13Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=4cd61c43fd513a8a0558db2d0d237d612e2d5e73'/>
<id>urn:sha1:4cd61c43fd513a8a0558db2d0d237d612e2d5e73</id>
<content type='text'>
Returning fabricated CRS value (0xFFFF0001) by PCIe Root Complex to OS is
allowed only for 4-byte PCI_VENDOR_ID config read request and only when
CRSSVE bit in Root Port PCIe device is enabled. In all other error PCIe
Root Complex must return all-ones.

So implement this logic in pci-aardvark.c driver properly.

aardvark HW does not have Root Port PCIe device and U-Boot does not
implement emulation of this device. So expect that CRSSVE bit is set as
U-Boot can already handle CRS value for PCI_VENDOR_ID config read request.

More callers of pci_bus_read_config() function in U-Boot do not check for
return value, but check readback value. Therefore always fill readback
value in pcie_advk_read_config() function. On error fill all-ones of
correct size as it is required for PCIe Root Complex.

And also correctly propagates error from failed config write request to
return value of pcie_advk_write_config() function. Most U-Boot callers
ignores this return value, but it is a good idea to return correct value
from function.

These issues about return value of failed config read requests, including
special handling of CRS were reported by Lorenzo and Bjorn for Linux kernel
driver pci-aardvark together with quotes from PCIe r4.0 spec, see details:
https://lore.kernel.org/linux-pci/20210624213345.3617-1-pali@kernel.org/t/#u

Signed-off-by: Pali Rohár &lt;pali@kernel.org&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>pci: ppc: Drop ftpci100 driver</title>
<updated>2021-08-06T12:26:48Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2021-08-02T00:54:40Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=22137b8d739b80fb4ffaaff4ec7d9966988b48c2'/>
<id>urn:sha1:22137b8d739b80fb4ffaaff4ec7d9966988b48c2</id>
<content type='text'>
This is not used in U-Boot at present. Drop it and related config options.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>pci: imx: Drop use of DM_PCI</title>
<updated>2021-08-05T23:46:35Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2021-08-02T00:54:31Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=2d88b26583ec0b4e98c999ae8c0c5c5f66ece1d3'/>
<id>urn:sha1:2d88b26583ec0b4e98c999ae8c0c5c5f66ece1d3</id>
<content type='text'>
Now that DM_PCI is always enabled we don't need to check it. Drop this
old code.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>pci: msc01: Drop use of DM_PCI</title>
<updated>2021-08-05T23:46:35Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2021-08-02T00:54:30Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0019e5e39f5651af3d8f0af82d445b09248e0f05'/>
<id>urn:sha1:0019e5e39f5651af3d8f0af82d445b09248e0f05</id>
<content type='text'>
Now that DM_PCI is always enabled we don't need to check it. Drop this
old code.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>pci: gt64120: Drop use of DM_PCI</title>
<updated>2021-08-05T23:46:35Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2021-08-02T00:54:29Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=4afab721f15f96152a5a16342c468cbf6e85272c'/>
<id>urn:sha1:4afab721f15f96152a5a16342c468cbf6e85272c</id>
<content type='text'>
Now that DM_PCI is always enabled we don't need to check it. Drop this
old code.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
</feed>
