u-boot.git/drivers/pci, branch v2023.07

pci: apple: Add support for M2 Pro/Max

2023-05-30T19:13:44Z

The PCIe controller on the M2 Pro/Max is different from the one found on earlier Apple SoCs. Some registers moved and te meaning of the bits in some other registers changed. But they are still similar enough to handle both controllers in the same driver. Signed-off-by: Mark Kettenis

pci: pcie_dw_rockchip: Support max_link_speed dts property

2023-05-17T09:36:18Z

Add support for max_link_speed specified in the PCI DT binding. Signed-off-by: Jon Lin [eugen.hristev@collabora.com: port to latest API, set default correctly, align to 80 chars] Signed-off-by: Eugen Hristev [jonas@kwiboo.se: switch to dev_read_u32_default] Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang

pci: pcie_dw_rockchip: Add rk3588 compatible

2023-05-17T09:36:18Z

Add compatible for RK3588 SoC. Signed-off-by: Jon Lin Reviewed-by: Kever Yang

pci: coreboot: Don't read regions when booting

2023-05-11T02:25:29Z

When U-Boot is the second-stage bootloader, PCI is already set up. We cannot read the regions from the device tree. There is no point anyway, since PCI devices have already been allocated according to the regions and it is not safe for U-Boot to make any changes. Signed-off-by: Simon Glass Reviewed-by: Bin Meng Fixes: f2ebaaa9f38d ("pci: Handle failed calloc in decode_regions()") Tested-by: Christian Gmeiner Tested-by: Bin Meng

pci: pcie_dw_rockchip: release resources on failing probe

2023-05-09T10:26:59Z

Implement a resource release mechanism on failing probe. Without this, a strange situation can happen e.g. when init port fails, or attempting to get the PHY fails, because the gpios have been requested first, and if the user tries to do 'pci enum' again, the driver will fail with 'can't find reset gpios' even if the gpios are there, just because they were blocked by a previous probe attempt. It is only natural to release the acquired resources if the probe fails, just for consistency if nothing else. This way on subsequent probe attempts, the user will get the same error message, and not something different that doesn't make sense. Signed-off-by: Eugen Hristev Reviewed-by: Kever Yang

drivers: use devfdt_get_addr_index_ptr when cast to pointer

2023-05-06T09:28:18Z

The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so use devfdt_get_addr_index_ptr instead of the devfdt_get_addr_index function in the various files in the drivers directory that cast to a pointer. As we are there also streamline the error response to -EINVAL on return. Signed-off-by: Johan Jonker Reviewed-by: Simon Glass

drivers: use devfdt_get_addr_size_index_ptr when cast to pointer

2023-05-06T09:28:18Z

The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so use devfdt_get_addr_size_index_ptr instead of the devfdt_get_addr_size_index function in the various files in the drivers directory that cast to a pointer. Signed-off-by: Johan Jonker Reviewed-by: Michael Trimarchi Reviewed-by: Simon Glass

drivers: use dev_read_addr_ptr when cast to pointer

2023-05-06T09:28:18Z

The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so use dev_read_addr_ptr instead of the dev_read_addr function in the various files in the drivers directory that cast to a pointer. As we are there also streamline the error response to -EINVAL on return. Signed-off-by: Johan Jonker Reviewed-by: Simon Glass

drivers: use dev_read_addr_index_ptr when cast to pointer

2023-05-06T09:28:18Z

The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so use dev_read_addr_index_ptr instead of the dev_read_addr_index function in the various files in the drivers directory that cast to a pointer. As we are there also streamline the error response to -EINVAL on return. Signed-off-by: Johan Jonker Reviewed-by: Michael Trimarchi Reviewed-by: Simon Glass

pci: layerscape: add support for kernel/official fsl, ls1088a-pcie binding

2023-05-05T01:46:03Z

This allows the Layerscape PCIe RC driver to use the upstream style binding (two "reg" entries instead of four). It is similar to the previous commit e10da1f985ad ("pci: layerscape: add official ls1028a binding support") which implemented this for the LS1028A. Signed-off-by: Mathew McBride Reviewed-by: Peng Fan Signed-off-by: Peng Fan Reviewed-by: Ioana Ciornei Tested-by: Ioana Ciornei # on LS1088A-RDB