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<title>u-boot.git/drivers/pci, branch v2023.10</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/pci?h=v2023.10</id>
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<updated>2023-08-12T01:59:18Z</updated>
<entry>
<title>pci: rockchip: Release resources on failing probe</title>
<updated>2023-08-12T01:59:18Z</updated>
<author>
<name>Jonas Karlman</name>
<email>jonas@kwiboo.se</email>
</author>
<published>2023-07-11T23:13:56Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0e2474f55001e00e966be50595e7e0e055255006'/>
<id>urn:sha1:0e2474f55001e00e966be50595e7e0e055255006</id>
<content type='text'>
The PCIe driver for RK3399 is affected by a similar issue that was fixed
for RK35xx in the commit e04b67a7f4c1 ("pci: pcie_dw_rockchip: release
resources on failing probe").

Resources are not released on failing probe, e.g. regulators may be left
enabled and the ep-gpio may be left in a requested state.

Change to use regulator_set_enable_if_allowed and disable regulators
after failure to keep regulator enable count balanced, ep-gpio is also
released on regulator failure.

Also add support for the vpcie12v-supply, remove unused include and
check return value from dev_read_addr_name.

Signed-off-by: Jonas Karlman &lt;jonas@kwiboo.se&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
</entry>
<entry>
<title>pci: plda: Get correct ECAM offset in multiple PCIe RC case</title>
<updated>2023-08-10T02:58:01Z</updated>
<author>
<name>Minda Chen</name>
<email>minda.chen@starfivetech.com</email>
</author>
<published>2023-08-07T08:53:35Z</published>
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<id>urn:sha1:8d184d4b652bad455e17d2d0e451c0e08e112f34</id>
<content type='text'>
Get the correct ECAM offset and record the secondary bus
number in Multiple RC case.

Signed-off-by: Minda Chen &lt;minda.chen@starfivetech.com&gt;
Reviewed-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
</content>
</entry>
<entry>
<title>starfive: pci: Add StarFive JH7110 pcie driver</title>
<updated>2023-08-02T03:02:32Z</updated>
<author>
<name>Mason Huo</name>
<email>mason.huo@starfivetech.com</email>
</author>
<published>2023-07-25T09:46:48Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7870a05581243b510f6a1feedce1243ddcd49637'/>
<id>urn:sha1:7870a05581243b510f6a1feedce1243ddcd49637</id>
<content type='text'>
Add pcie driver for StarFive JH7110, Also add PLDA
PCIe controller common driver functions.

Several devices are tested:
a) M.2 NVMe SSD
b) Realtek 8169 Ethernet adapter.

Signed-off-by: Mason Huo &lt;mason.huo@starfivetech.com&gt;
Signed-off-by: Minda Chen &lt;minda.chen@starfivetech.com&gt;
Acked-by: Pali Rohár &lt;pali@kernel.org&gt;
Reviewed-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
</content>
</entry>
<entry>
<title>spl: CONFIG_SPL_PCI_PNP should depend on CONFIG_SPL_PCI</title>
<updated>2023-07-30T16:52:30Z</updated>
<author>
<name>Heinrich Schuchardt</name>
<email>heinrich.schuchardt@canonical.com</email>
</author>
<published>2023-07-24T19:27:26Z</published>
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<id>urn:sha1:8d2c311ce64939fe829037e4ef7951c3fafaee06</id>
<content type='text'>
CONFIG_SPL_PCI_PNP=y without CONFIG_SPL_PCI=y makes no sense.

Fixes: 32f5e9e5c1a7 ("nvme: pci: Enable for SPL")
Signed-off-by: Heinrich Schuchardt &lt;heinrich.schuchardt@canonical.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>pci: pcie_dw_rockchip: Disable unused BARs of the root complex</title>
<updated>2023-07-28T10:45:03Z</updated>
<author>
<name>Jon Lin</name>
<email>jon.lin@rock-chips.com</email>
</author>
<published>2023-07-22T13:30:20Z</published>
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<id>urn:sha1:bc6b94b5788677c3633e0331203578ffa706ff4b</id>
<content type='text'>
The Root Complex BARs default to claim the full 1 GiB memory region on
RK3568, leaving no space for any attached device.

Fix this by disable the unused BAR 0 and BAR 1 of the RC.

Signed-off-by: Jon Lin &lt;jon.lin@rock-chips.com&gt;
[jonas@kwiboo.se: Move to rk_pcie_configure and use PCI_BASE_ADDRESS_0/1 const]
Signed-off-by: Jonas Karlman &lt;jonas@kwiboo.se&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
</entry>
<entry>
<title>pci: pcie_dw_rockchip: Speed up link probe</title>
<updated>2023-07-28T10:45:03Z</updated>
<author>
<name>Jonas Karlman</name>
<email>jonas@kwiboo.se</email>
</author>
<published>2023-07-22T13:30:19Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7ce186ada2ce1ece344dacc20244fb91866e435b'/>
<id>urn:sha1:7ce186ada2ce1ece344dacc20244fb91866e435b</id>
<content type='text'>
Use a similar pattern and delay values as the linux mainline driver to
speed up failing when nothing is connected.

Reduce fail speed from around 5+ seconds down to around one second on a
Radxa ROCK 3 Model A, where pcie2x1 is probed before pcie3x2 M2 slot.

Signed-off-by: Jonas Karlman &lt;jonas@kwiboo.se&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
</entry>
<entry>
<title>pci: pcie_dw_rockchip: Use regulator_set_enable_if_allowed</title>
<updated>2023-07-28T10:45:03Z</updated>
<author>
<name>Jonas Karlman</name>
<email>jonas@kwiboo.se</email>
</author>
<published>2023-07-22T13:30:18Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=8b001ee59a9d4a6246098c8bc5bb894a752e7c0b'/>
<id>urn:sha1:8b001ee59a9d4a6246098c8bc5bb894a752e7c0b</id>
<content type='text'>
The vpcie3v3 regulator is typically a fixed regulator controlled using
gpio. Change to use enable and disable calls on the regulator instead
of trying to set a voltage value.

Also remove the delay to match linux driver, for a fixed regulator the
startup-delay-us prop can be used in case a startup delay is needed.
Limited testing on ROCK 3A, ROCK 5B, Quartz64, Odroid-M1 has shown that
this delay was not needed.

Signed-off-by: Jonas Karlman &lt;jonas@kwiboo.se&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
</entry>
<entry>
<title>pci: pcie_dw_rockchip: Get config region from reg prop</title>
<updated>2023-07-28T10:45:03Z</updated>
<author>
<name>Jonas Karlman</name>
<email>jonas@kwiboo.se</email>
</author>
<published>2023-07-22T13:30:16Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=bed7b2f00b1346f712f849d53c72fa8642601115'/>
<id>urn:sha1:bed7b2f00b1346f712f849d53c72fa8642601115</id>
<content type='text'>
Get the config region to use from the reg prop. Also update the
referenced region index used in comment.

Signed-off-by: Jonas Karlman &lt;jonas@kwiboo.se&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
</entry>
<entry>
<title>pci: Mask the ROM address in case it is already enabled</title>
<updated>2023-07-17T09:12:26Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2023-07-16T03:39:03Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=fa5690c1f53929b78f9d9f4e270bd64befcda755'/>
<id>urn:sha1:fa5690c1f53929b78f9d9f4e270bd64befcda755</id>
<content type='text'>
In some cases the video ROM may have been enabled previously, such as by
a previous firmware stage. Use the correct address in that case.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>pci: Adjust video BIOS debugging to be SPL-friendly</title>
<updated>2023-07-17T09:12:26Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2023-07-16T03:39:02Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b7d4df5a04733c19747de80b9dfdfdee58c9850d'/>
<id>urn:sha1:b7d4df5a04733c19747de80b9dfdfdee58c9850d</id>
<content type='text'>
A hex value is expected for the VGA mode. Add a 0x prefix, since the #
construct is not supported in SPL. We don't want to add it, due to
code-size constraints.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
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