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<title>u-boot.git/drivers/pci, branch v2025.04</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/pci?h=v2025.04</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/pci?h=v2025.04'/>
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<updated>2025-01-23T18:11:49Z</updated>
<entry>
<title>pci: mediatek: add support for multiple ports in mediatek pcie gen3 driver</title>
<updated>2025-01-23T18:11:49Z</updated>
<author>
<name>Weijie Gao</name>
<email>weijie.gao@mediatek.com</email>
</author>
<published>2025-01-17T09:18:11Z</published>
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<id>urn:sha1:dfbadb86b3bc43c004671ab6eb46ee160a192e98</id>
<content type='text'>
One MediaTek PCIe Gen3 controller has only one port, where PCI bus 0
on this port represents the controller itself and bus 1 represents
the external PCIe device.

If multiple PCIe controllers are probed in U-Boot, U-Boot will use
bus numbers greater than 2 as input parameters. Therefore, we should
convert the BDF bus number to either 0 or 1 by subtracting the
offset by controller-&gt;seq_.

Signed-off-by: Sam Shih &lt;sam.shih@mediatek.com&gt;
Signed-off-by: Weijie Gao &lt;weijie.gao@mediatek.com&gt;
</content>
</entry>
<entry>
<title>Merge patch series "upl: Prerequite patches for updated spec"</title>
<updated>2025-01-22T23:08:47Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2025-01-22T22:08:34Z</published>
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<id>urn:sha1:a3b71cc6f5cc74d4edc5808790a3d2999ea3f7fe</id>
<content type='text'>
Simon Glass &lt;sjg@chromium.org&gt; says:

The current UPL spec[1] has been tidied up and improved over the last
year, since U-Boot's original UPL support was written.

This series includes some prerequisite patches needed for the real UPL
patches. It is split from [2]

[1] https://github.com/UniversalPayload/spec/tree/3f1450d
[2] https://patchwork.ozlabs.org/project/uboot/list/?series=438574&amp;state=*

Link: https://lore.kernel.org/r/20250111000029.245022-1-sjg@chromium.org
</content>
</entry>
<entry>
<title>pci: video: Set up the pixel-format field</title>
<updated>2025-01-22T23:08:23Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2025-01-11T00:00:19Z</published>
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<id>urn:sha1:97425461e7be88c047f7acb3d701c74cf2acac39</id>
<content type='text'>
Add this information to the handoff structure so that it is available to
U-Boot proper. Update bochs and the video handoff.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>pci: Add support for Qualcomm PCIe controller</title>
<updated>2025-01-22T15:43:54Z</updated>
<author>
<name>Neil Armstrong</name>
<email>neil.armstrong@linaro.org</email>
</author>
<published>2024-11-25T09:46:17Z</published>
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<id>urn:sha1:5b7ec7fb4437e3e9b50127114a59796a90c1681a</id>
<content type='text'>
Add support for the PCIe busses on Qualcomm platforms,
by using the pcie_dw_common infrastructure.

The driver is based on the Linux driver but only supporting
the "1_9_0" and compatible platforms like:
- sa8540p
- sc7280
- sc8180x
- sc8280xp
- sdm845
- sdx55
- sm8150
- sm8250
- sm8350
- sm8450
- sm8550
- sm8650
- x1e80100

But it has only been tested on:
- sc7280
- sm8550
- sm8650
- x1e80100

It supports setting the IOMMU SID table for supported platforms.

Signed-off-by: Neil Armstrong &lt;neil.armstrong@linaro.org&gt;
Link: https://lore.kernel.org/r/20241125-topic-pcie-controller-v1-2-45c20070dd53@linaro.org
Signed-off-by: Caleb Connolly &lt;caleb.connolly@linaro.org&gt;
</content>
</entry>
<entry>
<title>pci: pcie_dw_common: introduce pcie_dw_find_capability()</title>
<updated>2025-01-22T15:43:53Z</updated>
<author>
<name>Neil Armstrong</name>
<email>neil.armstrong@linaro.org</email>
</author>
<published>2024-11-25T09:46:16Z</published>
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<id>urn:sha1:aeeebdadc56ea2fde479e8b890019ca8cdbc9073</id>
<content type='text'>
Add PCIe config space capability search function specific for
the host controller, which are bridges *to* PCI devices but
are not PCI devices themselves.

Signed-off-by: Neil Armstrong &lt;neil.armstrong@linaro.org&gt;
Link: https://lore.kernel.org/r/20241125-topic-pcie-controller-v1-1-45c20070dd53@linaro.org
Signed-off-by: Caleb Connolly &lt;caleb.connolly@linaro.org&gt;
</content>
</entry>
<entry>
<title>Merge tag 'v2025.01-rc5' into next</title>
<updated>2024-12-26T04:31:04Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-12-26T04:31:04Z</published>
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<id>urn:sha1:5cfbf8c3644cc95c3c8b5d2541ed7f32136c0da1</id>
<content type='text'>
Prepare v2025.01-rc5
</content>
</entry>
<entry>
<title>pcie: starfive: Make the driver compatible with upstream DT</title>
<updated>2024-12-18T05:19:15Z</updated>
<author>
<name>Hal Feng</name>
<email>hal.feng@starfivetech.com</email>
</author>
<published>2024-12-08T09:19:34Z</published>
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<id>urn:sha1:0b7bf26d066d76ce2c357ec3bfbad09c399b455b</id>
<content type='text'>
There are difference between upstream DT and the old DT
in terms of reg base, reset gpio and syscon. Make the driver
compatible with upstream DT.

Tested-by: Anand Moon &lt;linux.amoon@gmail.com&gt;
Tested-by: E Shattow &lt;lucent@gmail.com&gt;
Signed-off-by: Hal Feng &lt;hal.feng@starfivetech.com&gt;
</content>
</entry>
<entry>
<title>pci: renesas: Fix R-Car spelling</title>
<updated>2024-12-11T07:36:24Z</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut+renesas@mailbox.org</email>
</author>
<published>2024-12-11T07:30:32Z</published>
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<id>urn:sha1:7246f98d29aba5d6caff230b427e39e219165fce</id>
<content type='text'>
The correct spelling is R-Car, including the dash, update the usage.
Kconfig strings and comment changes only, no functional change.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt;
</content>
</entry>
<entry>
<title>Merge patch series "Implement ACPI on aarch64"</title>
<updated>2024-10-28T00:44:13Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-10-27T23:14:22Z</published>
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<id>urn:sha1:2800aecce08b47b169d8e9824dd23b1297b2cedc</id>
<content type='text'>
Patrick Rudolph &lt;patrick.rudolph@9elements.com&gt; says:

Based on the existing work done by Simon Glass this series adds
support for booting aarch64 devices using ACPI only.
As first target QEMU SBSA support is added, which relies on ACPI
only to boot an OS. As secondary target the Raspberry Pi4 was used,
which is broadly available and allows easy testing of the proposed
solution.

The series is split into ACPI cleanups and code movements, adding
Arm specific ACPI tables and finally SoC and mainboard related
changes to boot a Linux on the QEMU SBSA and RPi4. Currently only the
mandatory ACPI tables are supported, allowing to boot into Linux
without errors.

The QEMU SBSA support is feature complete and provides the same
functionality as the EDK2 implementation.

The changes were tested on real hardware as well on QEMU v9.0:

qemu-system-aarch64 -machine sbsa-ref -nographic -cpu cortex-a57 \
                    -pflash secure-world.rom \
                    -pflash unsecure-world.rom

qemu-system-aarch64 -machine raspi4b -kernel u-boot.bin -cpu cortex-a72 \
-smp 4 -m 2G -drive file=raspbian.img,format=raw,index=0 \
-dtb bcm2711-rpi-4-b.dtb -nographic

Tested against FWTS V24.03.00.

Known issues:
- The QEMU rpi4 support is currently limited as it doesn't emulate PCI,
  USB or ethernet devices!
- The SMP bringup doesn't work on RPi4, but works in QEMU (Possibly
  cache related).
- PCI on RPI4 isn't working on real hardware since the pcie_brcmstb
  Linux kernel module doesn't support ACPI yet.

Link: https://lore.kernel.org/r/20241023132116.970117-1-patrick.rudolph@9elements.com
</content>
</entry>
<entry>
<title>arm: mach-bcm283x: Bring in some header files from tianocore</title>
<updated>2024-10-27T23:24:13Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2024-10-23T13:20:10Z</published>
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<id>urn:sha1:69a5616f06f1b2a98ca7294f4473bf5a832de230</id>
<content type='text'>
These header files presumably duplicate things already in the U-Boot
devicetree. For now, bring them in to get the ASL code and ACPI table
code to compile.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Patrick Rudolph &lt;patrick.rudolph@9elements.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Acked-by: Matthias Brugger &lt;mbrugger@suse.com&gt;
Cc: Matthias Brugger &lt;mbrugger@suse.com&gt;
Cc: Peter Robinson &lt;pbrobinson@gmail.com&gt;
Cc: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
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