u-boot.git/drivers/pci, branch v2025.10

pci: pcie-rcar-gen4: Add missing 1ms delay after PWR reset assertion

2025-09-25T21:19:17Z

R-Car V4H Reference Manual R19UH0186EJ0130 Rev.1.30 Apr. 21, 2025 page 585 Figure 9.3.2 Software Reset flow (B) indicates that for peripherals in HSC domain, after reset has been asserted by writing a matching reset bit into register SRCR, it is mandatory to wait 1ms. Because it is the controller driver which can determine whether or not the controller is in HSC domain based on its compatible string, add the missing delay into the controller driver. This 1ms delay is documented on R-Car V4H and V4M, it is currently unclear whether S4 is affected as well. This patch does apply the extra delay on R-Car S4 as well. Signed-off-by: Marek Vasut

pci: pcie-rcar-gen4: Assure reset occurs before DBI access

2025-09-25T21:19:17Z

Assure the reset is latched and the core is ready for DBI access. On R-Car V4H, the PCIe reset is asynchronized and does not take effect immediately, but needs a short time to complete. In case DBI access happens in that short time, that access generates an SError. Make sure that condition can never happen, read back the state of the reset which should turn the asynchronized reset into synchronized one, and wait a little over 1ms to add additional safety margin. Signed-off-by: Marek Vasut

pci: pcie-rcar-gen4: Fix inverted break condition in PHY initialization

2025-09-25T21:19:17Z

R-Car V4H Reference Manual R19UH0186EJ0130 Rev.1.30 Apr. 21, 2025 page 4581 Figure 104.3b Initial Setting of PCIEC(example), third quarter of the figure indicates that register 0xf8 should be polled until bit 18 becomes set to 1. Register 0xf8 bit 18 is 0 immediately after write to PCIERSTCTRL1 and is set to 1 in less than 1 ms afterward. The current readl_poll_timeout() break condition is inverted and returns when register 0xf8 bit 18 is set to 0, which in most cases means immediately. In case CONFIG_DEBUG_LOCK_ALLOC=y , the timing changes just enough for the first readl_poll_timeout() poll to already read register 0xf8 bit 18 as 1 and afterward never read register 0xf8 bit 18 as 0, which leads to timeout and failure to start the PCIe controller. Fix this by inverting the poll condition to match the reference manual initialization sequence. Signed-off-by: Marek Vasut

pci: pcie-rcar-gen4: Fix PHY initialization

2025-08-17T12:41:23Z

R-Car V4H Reference Manual R19UH0186EJ0130 Rev.1.30 Apr. 21, 2025 page 4581 Figure 104.3b Initial Setting of PCIEC(example) middle of the figure indicates that fourth write into register 0x148 [2:0] is 0x3 or GENMASK(1, 0). The current code writes GENMASK(11, 0) which is a typo. Fix the typo. Fixes: be3dd0dc2fd9 ("pci: pcie-rcar-gen4: Add Renesas R-Car Gen4 DW PCIe controller driver") Signed-off-by: Marek Vasut

pci: Assign a default value on reads on error

2025-07-14T21:16:48Z

Many callers of PCI read functions do not check the return value for error before using the variable that should contain the value read were there not to be an error. However in the error case this variable is never assigned to and so will contain uninitialised data. To provide some certainty as to behaviour in the error case assign a default value of all bits set. This issue found by Smatch. Signed-off-by: Andrew Goodbody

pci: pcie-rcar-gen4: Add Renesas R-Car Gen4 DW PCIe controller driver

2025-06-27T14:25:56Z

Add R-Car Gen4 PCIe controller support for host mode. This controller is based on Synopsys DesignWare PCIe. However, this particular controller has a number of vendor-specific registers, and as such, requires initialization code, including PHY firmware loading. The PHY firmware loading is implemented in an entirely generic manner, by calling a firmware loading script, which the user can configure in a way they require. This provides the user with flexibility of loading the PCIe firmware from whichever storage device they need to load it from. Signed-off-by: Marek Vasut

pci: pcie_dw_rockchip: Use dw_pcie_link_set_max_link_width()

2025-06-27T14:25:56Z

Use dw_pcie_link_set_max_link_width() instead of local implementation of the same functionality. This does change the behavior slightly, as the dw_pcie_link_set_max_link_width() implementation also programs the LNKCAP register MLW, this should however be correct and is now aligned with Linux kernel behavior. Signed-off-by: Marek Vasut

pci: pcie_dw_qcom: Use dw_pcie_link_set_max_link_width()

2025-06-27T14:25:56Z

Use dw_pcie_link_set_max_link_width() instead of local implementation of the same functionality. Signed-off-by: Marek Vasut Reviewed-by: Neil Armstrong

pci: pcie_dw_meson: Use dw_pcie_link_set_max_link_width()

2025-06-27T14:25:56Z

drivers: pci: pcie_dw_common: Add dw_pcie_link_set_max_link_width()

2025-06-27T14:25:56Z

Add dw_pcie_link_set_max_link_width() implementation ported from Linux kernel as of commit 89db0793c9f2 ("PCI: dwc: Add missing PCI_EXP_LNKCAP_MLW handling"). This is common code which is already duplicated in multiple drivers. Signed-off-by: Marek Vasut