In case the link is down, or the controller driver is removed before
booting the next stage, shut down the PCIe link, put both the remote
PCIe device and the controller into reset, and disable clock. This
way, the hardware is not left active when not in use.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

Correct the memory and IO mbus windows size increments in mvebu_pcie_bind.

Currently, pcie1 controller resource_size(&mem) and resource_size(&io)
checks result in a failure. This is because mem.end and io.end must be
incremented at the end of pcie0 windows assignment.

Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <stefan.roese@mailbox.org>

This driver has never been enabled by a platform since introduction and
does not currently compile. Remove it.

Signed-off-by: Tom Rini <trini@konsulko.com>

SoCFPGA updates for v2025.10:

CI: https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/27762

This pull request brings a set of updates across SoCFPGA platforms
covering Agilex5, Agilex7, N5X, and Stratix10. The changes include:

* Agilex5 enhancements:
  - USB3.1 enablement and DWC3 host driver support
  - System Manager register configuration for USB3
  - Watchdog timeout increase and SDMMC clock API integration
  - dcache handling improvements in SMC mailbox path
  - Enable SPL_SYS_DCACHE_OFF in defconfig

* Clock driver improvements:
  - Introduce dt-bindings header for Agilex clocks
  - Add enable/disable API and EMAC clock selection fixes
  - Replace manual shifts with FIELD_GET usage

* DDR updates:
  - IOSSM mailbox compatibility check
  - Correct DDR calibration status handling

* Device tree changes:
  - Agilex5: disable cache allocation for reads
  - Stratix10: add NAND IP node
  - Enable driver model watchdog
  - Enable USB3.1 node for Agilex5

* Config cleanups:
  - Simplify Agilex7 VAB defconfig
  - Remove obsolete SYS_BOOTM_LEN from N5X VAB config
  - Enable CRC32 support for SoCFPGA
  - Increase USB hub debounce timeout

Overall this set improves reliability of DDR and cache flows,
adds missing USB and MMC features for Agilex5, and refines clock
and configuration handling across platforms.

This patch set has been tested on Agilex 5 devkit, and Agilex devkit.

R-Car V4H Reference Manual R19UH0186EJ0130 Rev.1.30 Apr. 21, 2025 page 585
Figure 9.3.2 Software Reset flow (B) indicates that for peripherals in HSC
domain, after reset has been asserted by writing a matching reset bit into
register SRCR, it is mandatory to wait 1ms.

Because it is the controller driver which can determine whether or not the
controller is in HSC domain based on its compatible string, add the missing
delay into the controller driver.

This 1ms delay is documented on R-Car V4H and V4M, it is currently unclear
whether S4 is affected as well. This patch does apply the extra delay on
R-Car S4 as well.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

Assure the reset is latched and the core is ready for DBI access.
On R-Car V4H, the PCIe reset is asynchronized and does not take
effect immediately, but needs a short time to complete. In case
DBI access happens in that short time, that access generates an
SError. Make sure that condition can never happen, read back the
state of the reset which should turn the asynchronized reset into
synchronized one, and wait a little over 1ms to add additional
safety margin.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

R-Car V4H Reference Manual R19UH0186EJ0130 Rev.1.30 Apr. 21, 2025 page 4581
Figure 104.3b Initial Setting of PCIEC(example), third quarter of the figure
indicates that register 0xf8 should be polled until bit 18 becomes set to 1.

Register 0xf8 bit 18 is 0 immediately after write to PCIERSTCTRL1 and is set
to 1 in less than 1 ms afterward. The current readl_poll_timeout() break
condition is inverted and returns when register 0xf8 bit 18 is set to 0,
which in most cases means immediately. In case CONFIG_DEBUG_LOCK_ALLOC=y ,
the timing changes just enough for the first readl_poll_timeout() poll to
already read register 0xf8 bit 18 as 1 and afterward never read register
0xf8 bit 18 as 0, which leads to timeout and failure to start the PCIe
controller.

Fix this by inverting the poll condition to match the reference manual
initialization sequence.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/27684

- Add i.MX8 ahab-commit command.
- Add support for flashing board with UUU on imx93_frdm.
- Fix the acces of PFUZE100 regulator desc.
- Add more i.MX6 PWM clock definitions.
- Enable OP-TEE on phytec-imx8m and update documentation.
- Enable PCI host controller on iMX95 19x19 EVK.

[trini: Fixup spacing issues]
Signed-off-by: Tom Rini <trini@konsulko.com>

Adding iMX95/iMX94 support to the dw driver. Follow kernel driver
stype to use flags to distinguish the characteristic of different
platforms.

Signed-off-by: Ye Li <ye.li@nxp.com>

Wirting to command register should use PCI_COMMAND not PCI_PRIMARY_BUS

Signed-off-by: Ye Li <ye.li@nxp.com>