u-boot.git/drivers/pci, branch v2026.07

pci: brcmstb: Adapt to AXI bridge

2026-06-04T09:50:04Z

Fix-ups for the BCM root complex when it is located behind an AXI bridge and clocked with 54MHz. Some are from kernel commit 377bced88c326, some where picked by Oleksii off a now-stale older branch. All reworked for the simpler setup code in U-Boot. Signed-off-by: Torsten Duwe Co-authored-by: Oleksii Moisieiev Tested-by: Pedro Falcato Reviewed-by: Neil Armstrong

pci: brcmstb: rework iBAR handling

2026-06-04T09:50:04Z

Rework the setup of inbound PCIe windows: use the convenience functions from Linux kernel commit ae6476c6de187 to calculate the BAR offsets and factor out the setup code into a separate function. The Linux kernel first allocates and populates an array of inbound_win[] and sets the BARs from it later, while U-Boot does it all on the fly, in one go, so the code is not 1:1 comparable. Signed-off-by: Torsten Duwe Tested-by: Pedro Falcato Reviewed-by: Neil Armstrong

pci: brcmstb: Fix iBAR size calculation

2026-06-04T09:50:04Z

Fix inbound window size calculation, like Linux commit 25a98c7270156. Signed-off-by: Torsten Duwe Tested-by: Pedro Falcato Reviewed-by: Neil Armstrong

pci: brcmstb: Get and use bridge and rescal reset properties

2026-06-04T09:50:04Z

Check whether the device tree has nodes for the two reset controls and use them if so. Signed-off-by: Torsten Duwe Co-authored-by: Oleksii Moisieiev Tested-by: Pedro Falcato Reviewed-by: Neil Armstrong

pci: brcmstb: Support different variants using a cfg struct

2026-06-04T09:50:04Z

The Linux kernel driver already had support for multiple hardware variants when the bcm2712 was added (see e.g. linux commit 10dbedad3c818 which is the last in a longer set of changes). This patch brings in this required infrastructure and adds a differentiation between 2711 and 2712 register layouts on top. Signed-off-by: Torsten Duwe Co-authored-by: Oleksii Moisieiev Tested-by: Pedro Falcato Reviewed-by: Neil Armstrong

pci: brcmstb: Fix PCIe bus numbers

2026-06-04T09:50:04Z

The linux kernel assigns a new domain for every Root Complex where bus numbering starts from 0 for each domain. U-Boot does not have domains and uses a flattened bus numbering scheme instead. This means that any device or bridge on the second enumerated RC will receive a bus number equal to the last assigned one +1. This bus number contributes to the address written into the index register, which will select the configuration space to be read. Compensate for this contribution by subtracting the base bus number. Signed-off-by: Andrea della Porta Signed-off-by: Torsten Duwe Tested-by: Pedro Falcato Reviewed-by: Peter Robinson

pci: correct PCI device enumeration to include all functions on device 0

2026-04-27T17:11:08Z

Currently the implementation does not just skip all devices beside device 0, it also skips all functions (besides 0) on device 0. This broke basically all AMD platforms, since they have a lot of internal SOC devices behind these functions. This was detected, because the XHCI controller and therefore the USB devices were not found by u-boot on AMD/crater platform. PCI_MASK_BUS() returns both device and function bits, so it skips any bdf where either device > 0 or function > 0. Using PCI_DEV() extracts only the device number, matching the intent in only_one_child(). It therefore now checks all functions on device 0 (Linux does the same). I build tested u-boot as coreboot payload and run it on a recent x86 AMD platform. Devices like the XHCI controller are now found again. Fixes: fbde868ba4aa ("pci: skip unnecessary PCIe scanning") Signed-off-by: Maximilian Brune Reviewed-by: Simon Glass CC: Tom Rini CC: Andrew Goodbody CC: George McCollister CC: Simon Glass

pci: Add AMD Versal2 DW PCIe host controller driver

2026-04-23T09:49:48Z

Add support for the DesignWare-based PCIe host controller found in AMD Versal2 SoCs. This enables PCIe functionality (e.g. NVMe storage) on boards such as the VEK385. The driver builds on the existing pcie_dw_common infrastructure and adds Versal2-specific handling: it maps the SLCR register region to mask and clear TLP interrupt status bits, parses dbi/config/atu/slcr register regions from device tree, and supports an optional PERST# GPIO on child nodes for endpoint reset sequencing. The outbound iATU is programmed for the non-prefetchable memory window from device tree ranges. Signed-off-by: Pranav Sanwal Link: https://lore.kernel.org/r/20260327121015.996806-2-pranav.sanwal@amd.com Signed-off-by: Michal Simek

pci: imx: Properly support upstream Linux reset-gpios property

2026-04-02T12:05:06Z

The driver requests explicitly "reset-gpio" property, not the one with "gpios" suffix but upstream Linux kernel deprecated it in 2021. Existing upstream Linux kernel DTS is being changed to "reset-gpios" property, thus update the driver to read that one too. Note that driver is probably broken already, because it parsed GPIO in standard way respecting the flags and on top of that applied the "reset-gpio-active-high" flag, thus "reset-gpio ACTIVE_LOW" with the "reset-gpio-active-high" property would be double inverted. Signed-off-by: Krzysztof Kozlowski

pcie: starfive: Add a optional power gpio support

2026-03-16T17:36:57Z

Get and enable a optional power gpio. This feature is ported from the jh7110 pcie driver in Linux. VisionFive 2 Lite needs this gpio to enable the PCI bus device (M.2 M-Key) power. Signed-off-by: Hal Feng