<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/drivers/pci_auto.c, branch master</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>drivers/pci : move pci drivers to drivers/pci</title>
<updated>2007-11-24T19:35:55+00:00</updated>
<author>
<name>Jean-Christophe PLAGNIOL-VILLARD</name>
<email>plagnioj@jcrosoft.com</email>
</author>
<published>2007-11-20T19:28:09+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=93a686ee9c5ddc6fa368c32cfbfde6f6724599fc'/>
<id>93a686ee9c5ddc6fa368c32cfbfde6f6724599fc</id>
<content type='text'>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD &lt;plagnioj@jcrosoft.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD &lt;plagnioj@jcrosoft.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ppc4xx: (Re-)Enable CONFIG_PCI_PNP on AMCC 440EPx Sequoia</title>
<updated>2007-08-31T13:21:46+00:00</updated>
<author>
<name>Gary Jennejohn</name>
<email>garyj@denx.de</email>
</author>
<published>2007-08-31T13:21:46+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=81b73dec16fd1227369a191e725e10044a9d56b8'/>
<id>81b73dec16fd1227369a191e725e10044a9d56b8</id>
<content type='text'>
The 440EPx has a problem when the PCI_CACHE_LINE_SIZE register is
set to non-zero, because it doesn't support MRM (memory-read-
multiple) correctly. We now added the possibility to configure
this register in the board config file, so that the default value
of 8 can be overridden.

Here the details of this patch:

o drivers_pci_auto.c: introduce CFG_PCI_CACHE_LINE_SIZE to allow
  board-specific settings. As an example the sequoia board requires 0.
  Idea from Stefan Roese &lt;sr@denx.de&gt;.
o board/amcc/sequoia/init.S: add a TLB mapping at 0xE8000000 for the
  PCI IO-space. Obtained from Stefan Roese &lt;sr@denx.de&gt;.
o include/configs/sequoia.h: turn CONFIG_PCI_PNP back on and set
  CFG_PCI_CACHE_LINE_SIZE to 0.

Signed-off-by: Gary Jennejohn &lt;garyj@denx.de&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The 440EPx has a problem when the PCI_CACHE_LINE_SIZE register is
set to non-zero, because it doesn't support MRM (memory-read-
multiple) correctly. We now added the possibility to configure
this register in the board config file, so that the default value
of 8 can be overridden.

Here the details of this patch:

o drivers_pci_auto.c: introduce CFG_PCI_CACHE_LINE_SIZE to allow
  board-specific settings. As an example the sequoia board requires 0.
  Idea from Stefan Roese &lt;sr@denx.de&gt;.
o board/amcc/sequoia/init.S: add a TLB mapping at 0xE8000000 for the
  PCI IO-space. Obtained from Stefan Roese &lt;sr@denx.de&gt;.
o include/configs/sequoia.h: turn CONFIG_PCI_PNP back on and set
  CFG_PCI_CACHE_LINE_SIZE to 0.

Signed-off-by: Gary Jennejohn &lt;garyj@denx.de&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pciauto_setup_device bars_num fix</title>
<updated>2007-08-10T16:09:00+00:00</updated>
<author>
<name>Ed Swarthout</name>
<email>Ed.Swarthout@freescale.com</email>
</author>
<published>2007-07-27T06:50:44+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=936b3e69b667c3eb9a61ece4e78647d3fce9fc2a'/>
<id>936b3e69b667c3eb9a61ece4e78647d3fce9fc2a</id>
<content type='text'>
Passing bars_num=0 to pciauto_setup_device should assign no bars.

Signed-off-by: Ed Swarthout &lt;Ed.Swarthout@freescale.com&gt;
Acked-by: Shinya Kuribayashi &lt;shinya.kuribayashi@necel.com&gt;
Acked-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Passing bars_num=0 to pciauto_setup_device should assign no bars.

Signed-off-by: Ed Swarthout &lt;Ed.Swarthout@freescale.com&gt;
Acked-by: Shinya Kuribayashi &lt;shinya.kuribayashi@necel.com&gt;
Acked-by: Andy Fleming &lt;afleming@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Add simple agent/end-point configuration in PCI AutoConfig for PCI_CLASS_PROCESSOR_POWERPC.</title>
<updated>2007-07-11T21:43:40+00:00</updated>
<author>
<name>Ed Swarthout</name>
<email>Ed.Swarthout@freescale.com</email>
</author>
<published>2007-07-11T19:52:16+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5dc210dec5bace98a50b6ba905347890091a9bb0'/>
<id>5dc210dec5bace98a50b6ba905347890091a9bb0</id>
<content type='text'>
Signed-off-by: Ed Swarthout &lt;Ed.Swarthout@freescale.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Signed-off-by: Ed Swarthout &lt;Ed.Swarthout@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pciauto setup bridge</title>
<updated>2007-07-11T21:43:30+00:00</updated>
<author>
<name>Ed Swarthout</name>
<email>Ed.Swarthout@freescale.com</email>
</author>
<published>2007-07-11T19:52:08+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e8b85f3ba4cd8930e0a2fea2100c815d64201765'/>
<id>e8b85f3ba4cd8930e0a2fea2100c815d64201765</id>
<content type='text'>
The P2P bridge bus numbers programmed into the device are relative to
hose-&gt;first_busno.

Signed-off-by: Ed Swarthout &lt;Ed.Swarthout@freescale.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The P2P bridge bus numbers programmed into the device are relative to
hose-&gt;first_busno.

Signed-off-by: Ed Swarthout &lt;Ed.Swarthout@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Minor improvements to drivers/pci_auto.c</title>
<updated>2007-07-11T21:43:16+00:00</updated>
<author>
<name>Ed Swarthout</name>
<email>Ed.Swarthout@freescale.com</email>
</author>
<published>2007-07-11T19:51:48+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ba5feb12581bb2912ce301e4866b71f846e9fc07'/>
<id>ba5feb12581bb2912ce301e4866b71f846e9fc07</id>
<content type='text'>
- Make pciauto_{pre,post}scan_setup_bridge non-static
- Added physical address display in debug messages.

Signed-off-by: Ed Swarthout &lt;Ed.Swarthout@freescale.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
- Make pciauto_{pre,post}scan_setup_bridge non-static
- Added physical address display in debug messages.

Signed-off-by: Ed Swarthout &lt;Ed.Swarthout@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>[PATCH] Avoid assigning PCI resources from zero address</title>
<updated>2007-05-05T19:31:08+00:00</updated>
<author>
<name>Sergei Shtylyov</name>
<email>sshtylyov@ru.mvista.com</email>
</author>
<published>2007-04-23T13:30:39+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b7598a43f2b421a713d8135e98a42c37d9eb9df0'/>
<id>b7598a43f2b421a713d8135e98a42c37d9eb9df0</id>
<content type='text'>
If a PCI IDE card happens to get a zero address assigned to it, the Linux IDE
core complains and IDE drivers fails to work.  Also, assigning zero to a BAR
was illegal according to PCI 2.1 (the later revisions seem to have excluded the
sentence about "0" being considered an invalid address) -- so, use a reasonable
starting value of 0x1000 (that's what the most Linux archs are using).

Alternatively, one might have fixed the calls to pci_set_region() individually
(some code even seems to have taken care of this issue) but that would have
been a lot more work. :-)

Signed-off-by: Sergei Shtylyov &lt;sshtylyov@ru.mvista.com&gt;
Acked-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
If a PCI IDE card happens to get a zero address assigned to it, the Linux IDE
core complains and IDE drivers fails to work.  Also, assigning zero to a BAR
was illegal according to PCI 2.1 (the later revisions seem to have excluded the
sentence about "0" being considered an invalid address) -- so, use a reasonable
starting value of 0x1000 (that's what the most Linux archs are using).

Alternatively, one might have fixed the calls to pci_set_region() individually
(some code even seems to have taken care of this issue) but that would have
been a lot more work. :-)

Signed-off-by: Sergei Shtylyov &lt;sshtylyov@ru.mvista.com&gt;
Acked-by: Stefan Roese &lt;sr@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branch 'mpc85xx'</title>
<updated>2006-08-09T19:41:17+00:00</updated>
<author>
<name>Jon Loeliger</name>
<email>jdl@freescale.com</email>
</author>
<published>2006-08-09T19:41:17+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=92c427b18982167064de454ae5248ec466998919'/>
<id>92c427b18982167064de454ae5248ec466998919</id>
<content type='text'>
Conflicts:

	include/ft_build.h
	include/pci.h

Resolved, though.
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Conflicts:

	include/ft_build.h
	include/pci.h

Resolved, though.
</pre>
</div>
</content>
</entry>
<entry>
<title>* Made sure the code which disables prefetch for PCI devices sets the size of the prefetch region to 0 Patch by Andy Fleming on 17-Mar-2006</title>
<updated>2006-08-09T18:50:35+00:00</updated>
<author>
<name>Matthew McClintock</name>
<email>msm@freescale.com</email>
</author>
<published>2006-06-28T15:44:23+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a4e11558b810ef2cddffdf7b9d86bc1130441960'/>
<id>a4e11558b810ef2cddffdf7b9d86bc1130441960</id>
<content type='text'>
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Fix bug for io_bar size during pci scan</title>
<updated>2006-06-27T14:18:22+00:00</updated>
<author>
<name>Jin Zhengxiong-R64188</name>
<email>Jason.Jin@freescale.com</email>
</author>
<published>2006-06-27T10:12:02+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=bd22c2b97514fbfb0e03bd9c72b3445e4dbd57e2'/>
<id>bd22c2b97514fbfb0e03bd9c72b3445e4dbd57e2</id>
<content type='text'>
During the pci scan process, Some devices return bar_reponse with the
highest bytes 0, such as the pci bridge in uli1575 return bar_response
with 0xffffff, So the bar_size should be manually set under 64K.

Signed-off-by: Jason Jin &lt;jason.jin@freescale.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
During the pci scan process, Some devices return bar_reponse with the
highest bytes 0, such as the pci bridge in uli1575 return bar_response
with 0xffffff, So the bar_size should be manually set under 64K.

Signed-off-by: Jason Jin &lt;jason.jin@freescale.com&gt;
</pre>
</div>
</content>
</entry>
</feed>
