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<title>u-boot.git/drivers/pci_endpoint/Makefile, branch master</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/pci_endpoint/Makefile?h=master</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/pci_endpoint/Makefile?h=master'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2025-06-26T23:16:40Z</updated>
<entry>
<title>pci_endpoint: Add TI K3 Cadence PCIe Endpoint Controller driver</title>
<updated>2025-06-26T23:16:40Z</updated>
<author>
<name>Hrushikesh Salunke</name>
<email>h-salunke@ti.com</email>
</author>
<published>2025-06-16T16:49:28Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a4a0edc6046dd5b9ebe24ad72dfcdb43b36f0bd6'/>
<id>urn:sha1:a4a0edc6046dd5b9ebe24ad72dfcdb43b36f0bd6</id>
<content type='text'>
Add support for Endpoint mode of operation in the Cadence PCIe
Controller present on TI's K3 SoCs. This driver is an adaptation of the
Linux kernel v6.15 driver (drivers/pci/controller/cadence/pci-j721e.c).

Signed-off-by: Hrushikesh Salunke &lt;h-salunke@ti.com&gt;
</content>
</entry>
<entry>
<title>pci_ep: add pci endpoint sandbox driver</title>
<updated>2019-07-11T14:05:15Z</updated>
<author>
<name>Ramon Fried</name>
<email>ramon.fried@gmail.com</email>
</author>
<published>2019-04-27T08:15:23Z</published>
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<id>urn:sha1:bb413337826ef1a1445ff9fb33424fd231430228</id>
<content type='text'>
Add a dummy PCI endpoint for sandbox.
Supporting only a single function, it allows setting
and reading header configuration.

Signed-off-by: Ramon Fried &lt;ramon.fried@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>pci_ep: add Cadence PCIe endpoint driver</title>
<updated>2019-07-11T14:05:15Z</updated>
<author>
<name>Ramon Fried</name>
<email>ramon.fried@gmail.com</email>
</author>
<published>2019-04-27T08:15:22Z</published>
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<id>urn:sha1:c2ccc9e5cb9ac5547e063bc2bf35f6340b8f9362</id>
<content type='text'>
Add Cadence PCIe endpoint driver supporting configuration
of header, bars and MSI for device.

Signed-off-by: Ramon Fried &lt;ramon.fried@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>drivers: pci_ep: Introduce UCLASS_PCI_EP uclass</title>
<updated>2019-07-11T14:05:15Z</updated>
<author>
<name>Ramon Fried</name>
<email>ramon.fried@gmail.com</email>
</author>
<published>2019-04-27T08:15:21Z</published>
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<id>urn:sha1:914026d25848b856a669d629cb284c34843d707e</id>
<content type='text'>
Introduce new UCLASS_PCI_EP class for handling PCI endpoint
devices, allowing to set various attributes of the PCI endpoint
device, such as:
* configuration space header
* BAR definitions
* outband memory mapping
* start/stop PCI link

Signed-off-by: Ramon Fried &lt;ramon.fried@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
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