u-boot.git/drivers/pci_endpoint/Makefile, branch master Unnamed repository; edit this file 'description' to name the repository. pci_endpoint: Add TI K3 Cadence PCIe Endpoint Controller driver 2025-06-26T23:16:40+00:00 Hrushikesh Salunke h-salunke@ti.com 2025-06-16T16:49:28+00:00 a4a0edc6046dd5b9ebe24ad72dfcdb43b36f0bd6 Add support for Endpoint mode of operation in the Cadence PCIe Controller present on TI's K3 SoCs. This driver is an adaptation of the Linux kernel v6.15 driver (drivers/pci/controller/cadence/pci-j721e.c). Signed-off-by: Hrushikesh Salunke <h-salunke@ti.com> 
Add support for Endpoint mode of operation in the Cadence PCIe
Controller present on TI's K3 SoCs. This driver is an adaptation of the
Linux kernel v6.15 driver (drivers/pci/controller/cadence/pci-j721e.c).

Signed-off-by: Hrushikesh Salunke <h-salunke@ti.com>
pci_ep: add pci endpoint sandbox driver 2019-07-11T14:05:15+00:00 Ramon Fried ramon.fried@gmail.com 2019-04-27T08:15:23+00:00 bb413337826ef1a1445ff9fb33424fd231430228 Add a dummy PCI endpoint for sandbox. Supporting only a single function, it allows setting and reading header configuration. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> 
Add a dummy PCI endpoint for sandbox.
Supporting only a single function, it allows setting
and reading header configuration.

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
pci_ep: add Cadence PCIe endpoint driver 2019-07-11T14:05:15+00:00 Ramon Fried ramon.fried@gmail.com 2019-04-27T08:15:22+00:00 c2ccc9e5cb9ac5547e063bc2bf35f6340b8f9362 Add Cadence PCIe endpoint driver supporting configuration of header, bars and MSI for device. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> 
Add Cadence PCIe endpoint driver supporting configuration
of header, bars and MSI for device.

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
drivers: pci_ep: Introduce UCLASS_PCI_EP uclass 2019-07-11T14:05:15+00:00 Ramon Fried ramon.fried@gmail.com 2019-04-27T08:15:21+00:00 914026d25848b856a669d629cb284c34843d707e Introduce new UCLASS_PCI_EP class for handling PCI endpoint devices, allowing to set various attributes of the PCI endpoint device, such as: * configuration space header * BAR definitions * outband memory mapping * start/stop PCI link Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> 
Introduce new UCLASS_PCI_EP class for handling PCI endpoint
devices, allowing to set various attributes of the PCI endpoint
device, such as:
* configuration space header
* BAR definitions
* outband memory mapping
* start/stop PCI link

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>