u-boot.git/drivers/phy/Kconfig, branch v2024.01

phy: support Amlogic A1 family

2023-10-12T11:39:41Z

Setting G12A and A1 is similar, so we can use G12A phy driver with little changes. Signed-off-by: Alexey Romanov Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20231005085434.74755-6-avromanov@salutedevices.com Signed-off-by: Neil Armstrong

phy: Add support for the Apple Type-C PHY

2023-08-14T21:51:51Z

This is merely a dummy driver that makes sure the DWC3 XHCI driver finds its reset and PHY controllers. We rely on iBoot to set up the PHY for us. Signed-off-by: Mark Kettenis

phy: renesas: Add Renesas Ethernet SERDES driver for R-Car S4-8

2023-04-16T14:18:29Z

Add Renesas Ethernet SERDES driver for R-Car S4-8 (r8a779f0). The datasheet describes initialization procedure without any information about registers' name/bits. So, this is all black magic to initialize the hardware. Especially, all channels should be initialized at once. This driver is imported and adjusted from Linux 6.3-rc1 commit: 50133cd3e8dd1 ("phy: renesas: r8a779f0-eth-serdes: Remove retry code in .init()") Signed-off-by: Marek Vasut

phy: Move qcom SoCs specific phy drivers to qcom folder

2022-08-26T14:55:45Z

Signed-off-by: Sumit Garg

phy: mtk-tphy: add support for MediaTek MT7621 SoC

2022-07-13T21:03:37Z

This patch makes mtk-tphy driver available for MediaTek MT7621 SoC Signed-off-by: Weijie Gao

phy: nuvoton: add NPCM7xx phy control driver

2022-07-06T18:30:51Z

add BMC NPCM750 phy control driver Signed-off-by: Jim Liu

phy: phy-imx8mq-usb: Add support for i.MX8MP USB PHY

2022-04-12T15:33:56Z

Add initial support for i.MX8MP USB PHY, i.MX8MP USB is similar to the i.MX8MQ, except for clock and power domain design customization. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Peng Fan Cc: Stefano Babic Tested-By: Tim Harvey #imx8mp-venice-gw74xx

phy: zynqmp: Add serdes/psgtr driver

2022-01-12T09:41:46Z

Add PSGTR driver for Xilinx ZynqMP. The most of configurations are taken from Linux kernel psgtr driver. USB3.0 and SGMII configurations are tested on SOM. In SGMII case also IOU_SLCR reg is updated to get proper clock setup and signal detection configuration. Signed-off-by: Michal Simek Reviewed-by: Simon Glass Link: https://lore.kernel.org/r/36e6e9d3baf8511af1916e91e4887032ca2b6c20.1641458978.git.michal.simek@xilinx.com

phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC

2021-07-27T05:27:12Z

Add support for WIZ module present in TI's J721E SoC. WIZ is a SERDES wrapper used to configure some of the input signals to the SERDES. It is used with both Sierra(16G) and Torrent(10G) SERDES. This driver configures three clock selects (pll0, pll1, dig) and supports resets for each of the lanes. This is an adaptation of the linux driver. Signed-off-by: Jean-Jacques Hiblot Signed-off-by: Vignesh Raghavendra Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Lokesh Vutla Link: https://lore.kernel.org/r/20210721155849.20994-10-kishon@ti.com

phy: cadence: Add driver for Sierra PHY

2021-07-27T05:27:12Z

Add a Sierra PHY driver with PCIe and USB support. This driver is a port from the mainline linux driver. The PHY has multiple lanes, which can be configured into groups, and a generic PHY device is created for each group. There are two resets controlling the overall PHY block, one to enable the APB interface for programming registers, and another to enable the PHY itself. Additionally there are resets for each PHY lane. The PHY can be configured in hardware to read register settings from ROM, or they can be written by the driver. The sequence of operation on startup is to enable the APB bus, write the PHY registers (if required) for each lane group, and then enable the PHY. Each group of lanes can then be individually controlled using the power_on()/ power_off() function for that generic PHY One difference with the linux driver is that the PHY is always reset after it is powered-on. This is because role switching is not supported in u-boot and the cable orientation is handled by the PHY reset. Signed-off-by: Jean-Jacques Hiblot Signed-off-by: Alan Douglas Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Vignesh Raghavendra Signed-off-by: Lokesh Vutla Link: https://lore.kernel.org/r/20210721155849.20994-8-kishon@ti.com