u-boot.git/drivers/phy/Kconfig, branch v2024.07

phy: phy-imx8m-pcie: Add support for i.MX8M{M/P} PCIe PHY

2024-03-24T16:35:59Z

Add initial support for i.MX8M{M/P} PCIe PHY. On i.MX8M{M/P} SoCs PCIe PHY initialization moved to this standalone PHY driver. Inspired from counterpart Linux kernel v6.8-rc3 driver: drivers/phy/freescale/phy-fsl-imx8m-pcie.c. Use last Linux kernel driver reference commit 7559e7572c03 ("phy: Explicitly include correct DT includes"). Tested-by: Tim Harvey #imx8mp-venice* Tested-by: Adam Ford #imx8mp-beacon-kit Reviewed-by: Marek Vasut Signed-off-by: Sumit Garg

phy: support Amlogic A1 family

2023-10-12T11:39:41Z

Setting G12A and A1 is similar, so we can use G12A phy driver with little changes. Signed-off-by: Alexey Romanov Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20231005085434.74755-6-avromanov@salutedevices.com Signed-off-by: Neil Armstrong

phy: Add support for the Apple Type-C PHY

2023-08-14T21:51:51Z

This is merely a dummy driver that makes sure the DWC3 XHCI driver finds its reset and PHY controllers. We rely on iBoot to set up the PHY for us. Signed-off-by: Mark Kettenis

phy: renesas: Add Renesas Ethernet SERDES driver for R-Car S4-8

2023-04-16T14:18:29Z

Add Renesas Ethernet SERDES driver for R-Car S4-8 (r8a779f0). The datasheet describes initialization procedure without any information about registers' name/bits. So, this is all black magic to initialize the hardware. Especially, all channels should be initialized at once. This driver is imported and adjusted from Linux 6.3-rc1 commit: 50133cd3e8dd1 ("phy: renesas: r8a779f0-eth-serdes: Remove retry code in .init()") Signed-off-by: Marek Vasut

phy: Move qcom SoCs specific phy drivers to qcom folder

2022-08-26T14:55:45Z

Signed-off-by: Sumit Garg

phy: mtk-tphy: add support for MediaTek MT7621 SoC

2022-07-13T21:03:37Z

This patch makes mtk-tphy driver available for MediaTek MT7621 SoC Signed-off-by: Weijie Gao

phy: nuvoton: add NPCM7xx phy control driver

2022-07-06T18:30:51Z

add BMC NPCM750 phy control driver Signed-off-by: Jim Liu

phy: phy-imx8mq-usb: Add support for i.MX8MP USB PHY

2022-04-12T15:33:56Z

Add initial support for i.MX8MP USB PHY, i.MX8MP USB is similar to the i.MX8MQ, except for clock and power domain design customization. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Peng Fan Cc: Stefano Babic Tested-By: Tim Harvey #imx8mp-venice-gw74xx

phy: zynqmp: Add serdes/psgtr driver

2022-01-12T09:41:46Z

Add PSGTR driver for Xilinx ZynqMP. The most of configurations are taken from Linux kernel psgtr driver. USB3.0 and SGMII configurations are tested on SOM. In SGMII case also IOU_SLCR reg is updated to get proper clock setup and signal detection configuration. Signed-off-by: Michal Simek Reviewed-by: Simon Glass Link: https://lore.kernel.org/r/36e6e9d3baf8511af1916e91e4887032ca2b6c20.1641458978.git.michal.simek@xilinx.com

phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC

2021-07-27T05:27:12Z

Add support for WIZ module present in TI's J721E SoC. WIZ is a SERDES wrapper used to configure some of the input signals to the SERDES. It is used with both Sierra(16G) and Torrent(10G) SERDES. This driver configures three clock selects (pll0, pll1, dig) and supports resets for each of the lanes. This is an adaptation of the linux driver. Signed-off-by: Jean-Jacques Hiblot Signed-off-by: Vignesh Raghavendra Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Lokesh Vutla Link: https://lore.kernel.org/r/20210721155849.20994-10-kishon@ti.com