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<title>u-boot.git/drivers/phy/Kconfig, branch v2025.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/phy/Kconfig?h=v2025.07</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/phy/Kconfig?h=v2025.07'/>
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<updated>2025-03-19T02:36:19Z</updated>
<entry>
<title>phy: rcar: Support RZ/G2L USB PHY</title>
<updated>2025-03-19T02:36:19Z</updated>
<author>
<name>Paul Barker</name>
<email>paul.barker.ct@bp.renesas.com</email>
</author>
<published>2025-03-11T20:57:46Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5f7d61122f04f1f04f686e8b95984f1f9523d847'/>
<id>urn:sha1:5f7d61122f04f1f04f686e8b95984f1f9523d847</id>
<content type='text'>
Extend the existing Renesas R-Car Gen3 USB 2.0 PHY driver to support the
RZ/G2L and related SoCs.

Also enable this driver by default for the RZ/G2L SoC family.

Reviewed-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt;
Signed-off-by: Paul Barker &lt;paul.barker.ct@bp.renesas.com&gt;
</content>
</entry>
<entry>
<title>phy: starfive: Add Starfive JH7110 USB 2.0 PHY driver</title>
<updated>2025-03-17T00:55:18Z</updated>
<author>
<name>Minda Chen</name>
<email>minda.chen@starfivetech.com</email>
</author>
<published>2025-03-06T06:20:26Z</published>
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<id>urn:sha1:20281cc309acbddd6765fae03de1eed378aa5701</id>
<content type='text'>
Add Starfive JH7110 USB 2.0 PHY driver, which is generic
PHY driver.

Signed-off-by: Minda Chen &lt;minda.chen@starfivetech.com&gt;
Reviewed-by: Roger Quadros &lt;rogerq@kernel.org&gt;
Tested-by: E Shattow &lt;lucent@gmail.com&gt;
</content>
</entry>
<entry>
<title>phy: phy-mtk-tphy: add support for phy type switch</title>
<updated>2024-07-08T17:45:50Z</updated>
<author>
<name>Christian Marangi</name>
<email>ansuelsmth@gmail.com</email>
</author>
<published>2024-06-24T21:03:27Z</published>
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<id>urn:sha1:d4a489c1b21cba778600b441b59c8bcf2a879388</id>
<content type='text'>
Add support for PHY type switch via the mediatek topmisc syscon.

This is needed on mt7981 to make the PCIe correctly work and display
LinkUp.

Follow the same implementation done on Linux kernel with the usage of
the mediatek,syscon-type property.

Example:

u3port0: usb-phy@11e10700 {
	reg = &lt;0x11e10700 0x900&gt;;
	clocks = &lt;&amp;topckgen CK_TOP_USB3_PHY_SEL&gt;;
	clock-names = "ref";
	#phy-cells = &lt;1&gt;;
	mediatek,syscon-type = &lt;&amp;topmisc 0x218 0&gt;;
	status = "okay";
};

Signed-off-by: Christian Marangi &lt;ansuelsmth@gmail.com&gt;
</content>
</entry>
<entry>
<title>phy: phy-imx8m-pcie: Add support for i.MX8M{M/P} PCIe PHY</title>
<updated>2024-03-24T16:35:59Z</updated>
<author>
<name>Sumit Garg</name>
<email>sumit.garg@linaro.org</email>
</author>
<published>2024-03-21T14:55:02Z</published>
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<id>urn:sha1:c214ebce09bcea4b827344526f55d7bd300046c3</id>
<content type='text'>
Add initial support for i.MX8M{M/P} PCIe PHY. On i.MX8M{M/P} SoCs PCIe
PHY initialization moved to this standalone PHY driver.

Inspired from counterpart Linux kernel v6.8-rc3 driver:
drivers/phy/freescale/phy-fsl-imx8m-pcie.c. Use last Linux kernel driver
reference commit 7559e7572c03 ("phy: Explicitly include correct DT
includes").

Tested-by: Tim Harvey &lt;tharvey@gateworks.com&gt; #imx8mp-venice*
Tested-by: Adam Ford &lt;aford173@gmail.com&gt; #imx8mp-beacon-kit
Reviewed-by: Marek Vasut &lt;marex@denx.de&gt;
Signed-off-by: Sumit Garg &lt;sumit.garg@linaro.org&gt;
</content>
</entry>
<entry>
<title>phy: support Amlogic A1 family</title>
<updated>2023-10-12T11:39:41Z</updated>
<author>
<name>Alexey Romanov</name>
<email>avromanov@salutedevices.com</email>
</author>
<published>2023-10-05T08:54:26Z</published>
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<id>urn:sha1:5533c883ce10b2dd98de6cd5b47cc97f6720577c</id>
<content type='text'>
Setting G12A and A1 is similar, so we can use G12A phy
driver with little changes.

Signed-off-by: Alexey Romanov &lt;avromanov@salutedevices.com&gt;
Reviewed-by: Neil Armstrong &lt;neil.armstrong@linaro.org&gt;
Link: https://lore.kernel.org/r/20231005085434.74755-6-avromanov@salutedevices.com
Signed-off-by: Neil Armstrong &lt;neil.armstrong@linaro.org&gt;
</content>
</entry>
<entry>
<title>phy: Add support for the Apple Type-C PHY</title>
<updated>2023-08-14T21:51:51Z</updated>
<author>
<name>Mark Kettenis</name>
<email>kettenis@openbsd.org</email>
</author>
<published>2023-07-14T20:21:42Z</published>
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<id>urn:sha1:b99c6357877da2829dc7fd73a50048e83abc53e2</id>
<content type='text'>
This is merely a dummy driver that makes sure the DWC3 XHCI driver
finds its reset and PHY controllers.  We rely on iBoot to set up
the PHY for us.

Signed-off-by: Mark Kettenis &lt;kettenis@openbsd.org&gt;
</content>
</entry>
<entry>
<title>phy: renesas: Add Renesas Ethernet SERDES driver for R-Car S4-8</title>
<updated>2023-04-16T14:18:29Z</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut+renesas@mailbox.org</email>
</author>
<published>2023-03-19T17:09:43Z</published>
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<id>urn:sha1:08c56144767372605236b564bea14c7833398043</id>
<content type='text'>
Add Renesas Ethernet SERDES driver for R-Car S4-8 (r8a779f0).
The datasheet describes initialization procedure without any information
about registers' name/bits. So, this is all black magic to initialize
the hardware. Especially, all channels should be initialized at once.

This driver is imported and adjusted from Linux 6.3-rc1 commit:
50133cd3e8dd1 ("phy: renesas: r8a779f0-eth-serdes: Remove retry code in .init()")

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt;
</content>
</entry>
<entry>
<title>phy: Move qcom SoCs specific phy drivers to qcom folder</title>
<updated>2022-08-26T14:55:45Z</updated>
<author>
<name>Sumit Garg</name>
<email>sumit.garg@linaro.org</email>
</author>
<published>2022-08-04T14:27:09Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=23ba5f34c8e13e65e8d3749bad610d56fc4814cc'/>
<id>urn:sha1:23ba5f34c8e13e65e8d3749bad610d56fc4814cc</id>
<content type='text'>
Signed-off-by: Sumit Garg &lt;sumit.garg@linaro.org&gt;
</content>
</entry>
<entry>
<title>phy: mtk-tphy: add support for MediaTek MT7621 SoC</title>
<updated>2022-07-13T21:03:37Z</updated>
<author>
<name>Weijie Gao</name>
<email>weijie.gao@mediatek.com</email>
</author>
<published>2022-05-20T03:23:01Z</published>
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<id>urn:sha1:be3dc920988df180182f263524d536772cc16986</id>
<content type='text'>
This patch makes mtk-tphy driver available for MediaTek MT7621 SoC

Signed-off-by: Weijie Gao &lt;weijie.gao@mediatek.com&gt;
</content>
</entry>
<entry>
<title>phy: nuvoton: add NPCM7xx phy control driver</title>
<updated>2022-07-06T18:30:51Z</updated>
<author>
<name>Jim Liu</name>
<email>jim.t90615@gmail.com</email>
</author>
<published>2022-06-21T09:03:38Z</published>
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<id>urn:sha1:fdd08f896bcfc513a4cb7799d0094e4fabc73531</id>
<content type='text'>
add BMC NPCM750 phy control driver

Signed-off-by: Jim Liu &lt;JJLIU0@nuvoton.com&gt;
</content>
</entry>
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