u-boot.git/drivers/phy/Makefile, branch v2025.07 Unnamed repository; edit this file 'description' to name the repository. Kbuild: Always use $(PHASE_) 2025-04-11T18:16:44+00:00 Tom Rini trini@konsulko.com 2025-04-01T22:55:23+00:00 302b41d5397e9f821d360a74335e8821d4513970 It is confusing to have both "$(PHASE_)" and "$(XPL_)" be used in our Makefiles as part of the macros to determine when to do something in our Makefiles based on what phase of the build we are in. For consistency, bring this down to a single macro and use "$(PHASE_)" only. Signed-off-by: Tom Rini <trini@konsulko.com> 
It is confusing to have both "$(PHASE_)" and "$(XPL_)" be used in our
Makefiles as part of the macros to determine when to do something in our
Makefiles based on what phase of the build we are in. For consistency,
bring this down to a single macro and use "$(PHASE_)" only.

Signed-off-by: Tom Rini <trini@konsulko.com>
phy: starfive: Add Starfive JH7110 USB 2.0 PHY driver 2025-03-17T00:55:18+00:00 Minda Chen minda.chen@starfivetech.com 2025-03-06T06:20:26+00:00 20281cc309acbddd6765fae03de1eed378aa5701 Add Starfive JH7110 USB 2.0 PHY driver, which is generic PHY driver. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Tested-by: E Shattow <lucent@gmail.com> 
Add Starfive JH7110 USB 2.0 PHY driver, which is generic
PHY driver.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Tested-by: E Shattow <lucent@gmail.com>
global: Rename SPL_ to XPL_ 2024-10-11T17:44:48+00:00 Simon Glass sjg@chromium.org 2024-09-30T01:49:53+00:00 c46760d5967d12b6f7d37402878d1607a98b2b84 Use XPL_ as the symbol to indicate an SPL build. This means that SPL_ is no-longer set. Signed-off-by: Simon Glass <sjg@chromium.org> 
Use XPL_ as the symbol to indicate an SPL build. This means that SPL_ is
no-longer set.

Signed-off-by: Simon Glass <sjg@chromium.org>
phy: phy-imx8m-pcie: Add support for i.MX8M{M/P} PCIe PHY 2024-03-24T16:35:59+00:00 Sumit Garg sumit.garg@linaro.org 2024-03-21T14:55:02+00:00 c214ebce09bcea4b827344526f55d7bd300046c3 Add initial support for i.MX8M{M/P} PCIe PHY. On i.MX8M{M/P} SoCs PCIe PHY initialization moved to this standalone PHY driver. Inspired from counterpart Linux kernel v6.8-rc3 driver: drivers/phy/freescale/phy-fsl-imx8m-pcie.c. Use last Linux kernel driver reference commit 7559e7572c03 ("phy: Explicitly include correct DT includes"). Tested-by: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice* Tested-by: Adam Ford <aford173@gmail.com> #imx8mp-beacon-kit Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Sumit Garg <sumit.garg@linaro.org> 
Add initial support for i.MX8M{M/P} PCIe PHY. On i.MX8M{M/P} SoCs PCIe
PHY initialization moved to this standalone PHY driver.

Inspired from counterpart Linux kernel v6.8-rc3 driver:
drivers/phy/freescale/phy-fsl-imx8m-pcie.c. Use last Linux kernel driver
reference commit 7559e7572c03 ("phy: Explicitly include correct DT
includes").

Tested-by: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice*
Tested-by: Adam Ford <aford173@gmail.com> #imx8mp-beacon-kit
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
tree-wide: Replace http:// link with https:// link for ti.com 2023-11-10T16:01:50+00:00 Nishanth Menon nm@ti.com 2023-11-01T20:56:03+00:00 a94a4071d449e12c9fb5ac37d6362d22efcb27da Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com> 
Replace instances of http://www.ti.com with https://www.ti.com

Signed-off-by: Nishanth Menon <nm@ti.com>
phy: Add support for the Apple Type-C PHY 2023-08-14T21:51:51+00:00 Mark Kettenis kettenis@openbsd.org 2023-07-14T20:21:42+00:00 b99c6357877da2829dc7fd73a50048e83abc53e2 This is merely a dummy driver that makes sure the DWC3 XHCI driver finds its reset and PHY controllers. We rely on iBoot to set up the PHY for us. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> 
This is merely a dummy driver that makes sure the DWC3 XHCI driver
finds its reset and PHY controllers.  We rely on iBoot to set up
the PHY for us.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
phy: renesas: Add Renesas Ethernet SERDES driver for R-Car S4-8 2023-04-16T14:18:29+00:00 Marek Vasut marek.vasut+renesas@mailbox.org 2023-03-19T17:09:43+00:00 08c56144767372605236b564bea14c7833398043 Add Renesas Ethernet SERDES driver for R-Car S4-8 (r8a779f0). The datasheet describes initialization procedure without any information about registers' name/bits. So, this is all black magic to initialize the hardware. Especially, all channels should be initialized at once. This driver is imported and adjusted from Linux 6.3-rc1 commit: 50133cd3e8dd1 ("phy: renesas: r8a779f0-eth-serdes: Remove retry code in .init()") Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> 
Add Renesas Ethernet SERDES driver for R-Car S4-8 (r8a779f0).
The datasheet describes initialization procedure without any information
about registers' name/bits. So, this is all black magic to initialize
the hardware. Especially, all channels should be initialized at once.

This driver is imported and adjusted from Linux 6.3-rc1 commit:
50133cd3e8dd1 ("phy: renesas: r8a779f0-eth-serdes: Remove retry code in .init()")

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
phy: Move qcom SoCs specific phy drivers to qcom folder 2022-08-26T14:55:45+00:00 Sumit Garg sumit.garg@linaro.org 2022-08-04T14:27:09+00:00 23ba5f34c8e13e65e8d3749bad610d56fc4814cc Signed-off-by: Sumit Garg <sumit.garg@linaro.org> 
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
phy: nuvoton: add NPCM7xx phy control driver 2022-07-06T18:30:51+00:00 Jim Liu jim.t90615@gmail.com 2022-06-21T09:03:38+00:00 fdd08f896bcfc513a4cb7799d0094e4fabc73531 add BMC NPCM750 phy control driver Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> 
add BMC NPCM750 phy control driver

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
phy: zynqmp: Add serdes/psgtr driver 2022-01-12T09:41:46+00:00 Michal Simek michal.simek@xilinx.com 2022-01-06T08:49:41+00:00 1d78d68349621316ddff95a0d0d3ab9360061a9a Add PSGTR driver for Xilinx ZynqMP. The most of configurations are taken from Linux kernel psgtr driver. USB3.0 and SGMII configurations are tested on SOM. In SGMII case also IOU_SLCR reg is updated to get proper clock setup and signal detection configuration. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Link: https://lore.kernel.org/r/36e6e9d3baf8511af1916e91e4887032ca2b6c20.1641458978.git.michal.simek@xilinx.com 
Add PSGTR driver for Xilinx ZynqMP.
The most of configurations are taken from Linux kernel psgtr driver.

USB3.0 and SGMII configurations are tested on SOM. In SGMII case also
IOU_SLCR reg is updated to get proper clock setup and signal detection
configuration.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/r/36e6e9d3baf8511af1916e91e4887032ca2b6c20.1641458978.git.michal.simek@xilinx.com