u-boot.git/drivers/phy/allwinner, branch v2018.07

phy: sun4i-usb: Add a sunxi specific function for setting squelch-detect

2018-05-28T11:10:43Z

The sunxi otg phy has a bug where it wrongly detects a high speed squelch when reset on the root port gets de-asserted with a lo-speed device. The workaround for this is to disable squelch detect before de-asserting reset, and re-enabling it after the reset de-assert is done. Add a sunxi specific phy function to allow the sunxi-musb glue to do this. Signed-off-by: Jagan Teki Acked-by: Jun Nie

phy: sun4i-usb: Add A23 USB PHY config

2018-05-28T11:10:43Z

Allwinner A23 has 2 USB PHY's and 0x04 has phy ctrl offset. Signed-off-by: Jagan Teki Acked-by: Jun Nie

phy: sun4i-usb: Add A33 USB PHY config

2018-05-28T11:10:43Z

Allwinner A33 has 2 USB PHY's and 0x10 has phy ctrl offset. Signed-off-by: Jagan Teki Acked-by: Jun Nie

phy: sun4i-usb: Add A31 PHY config

2018-05-28T11:10:43Z

Allwinner A31 has 3 USB PHY's and rest similar to A10. Signed-off-by: Jagan Teki Acked-by: Jun Nie

phy: sun4i-usb: Add A10/A13/A20 PHY config

2018-05-28T11:10:43Z

Add PHY configs for Allwinner A10/A13/A20 which are SUN4I. Signed-off-by: Jagan Teki Acked-by: Jun Nie

phy: sun4i-usb: Add A83T USB PHY config

2018-05-28T11:10:43Z

Unlike, other Allwinner SUN4I Phy supporting SOC, A83T has 2 USB PHY's and second one is HSIC. So phy control need to configure to handle these HSIC and SIDDQ requirement. Signed-off-by: Jagan Teki Acked-by: Jun Nie

phy: sun4i-usb: Add V3S PHY config

2018-05-28T11:10:43Z

V3S has 1 USB PHY, rest are similar to A64. Signed-off-by: Jagan Teki Acked-by: Jun Nie

phy: sun4i-usb: Add H3/H5 PHY config

2018-05-28T11:10:43Z

H3/H5 has 4 USB PHY, rest are similar to A64. Signed-off-by: Jagan Teki Acked-by: Jun Nie

phy: sun4i-usb: Add id_detect and vbus_detect ops

2018-05-28T11:10:43Z

ID and VBUS detection code require when musb changing between Host and/or Peripheral modes. Signed-off-by: Jagan Teki Acked-by: Jun Nie

phy: Add Allwinner A64 USB PHY driver

2018-05-28T11:10:43Z

USB PHY implementation for Allwinner SOC's can be handling in to single driver with different phy configs. This driver handle all Allwinner USB PHY's start from 4I to 50I(except 9I). Currently added A64 compatibility more will add in next coming patches. Current implementation is unable to get pinctrl, clock and reset details from DT since the dm code on these will add it future. Driver named as phy-sun4i-usb.c since the same PHY logic work for all Allwinner SOC's start from 4I to A64 except 9I with different phy configurations. Signed-off-by: Jagan Teki Acked-by: Jun Nie