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<title>u-boot.git/drivers/phy/marvell, branch v2020.04</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/phy/marvell?h=v2020.04</id>
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<updated>2020-02-06T02:33:46Z</updated>
<entry>
<title>dm: core: Create a new header file for 'compat' features</title>
<updated>2020-02-06T02:33:46Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-02-03T14:36:16Z</published>
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<id>urn:sha1:336d4615f8fa774557d14f9b3245daa9e5fe3dbc</id>
<content type='text'>
At present dm/device.h includes the linux-compatible features. This
requires including linux/compat.h which in turn includes a lot of headers.
One of these is malloc.h which we thus end up including in every file in
U-Boot. Apart from the inefficiency of this, it is problematic for sandbox
which needs to use the system malloc() in some files.

Move the compatibility features into a separate header file.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>dm: core: Require users of devres to include the header</title>
<updated>2020-02-06T02:33:46Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2020-02-03T14:36:15Z</published>
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<id>urn:sha1:61b29b82683863a970fd4609a7c58512872616bc</id>
<content type='text'>
At present devres.h is included in all files that include dm.h but few
make use of it. Also this pulls in linux/compat which adds several more
headers. Drop the automatic inclusion and require files to include devres
themselves. This provides a good indication of which files use devres.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Anatolij Gustschin &lt;agust@denx.de&gt;
</content>
</entry>
<entry>
<title>phy: marvell: add SATA comphy RX/TX polarity invert support</title>
<updated>2018-09-19T11:54:27Z</updated>
<author>
<name>Rabeeh Khoury</name>
<email>rabeeh@solid-run.com</email>
</author>
<published>2018-09-06T09:37:48Z</published>
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<id>urn:sha1:d13b740ca621531fc3d86b33feed24592be0bd18</id>
<content type='text'>
This patch adds support to Armada 7k/8k comphy RX/TX lane swap. The
'phy-invert' DT property defines the inverted signals.

Signed-off-by: Rabeeh Khoury &lt;rabeeh@solid-run.com&gt;
Signed-off-by: Baruch Siach &lt;baruch@tkos.co.il&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>phy: marvell: Support changing SERDES map in board file</title>
<updated>2018-09-19T06:59:26Z</updated>
<author>
<name>Marek Behún</name>
<email>marek.behun@nic.cz</email>
</author>
<published>2018-08-17T10:58:51Z</published>
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<id>urn:sha1:4b8cb84327a448f16b276769e0ffbc7869d6de4a</id>
<content type='text'>
This adds a weak definition of comphy_update_map to comphy_core,
which does nothing. If this function is defined elsewhere, for example
in board file, the board file can change some parameters of SERDES
configuration.

This is needed on Turris Mox, where the SERDES speed on lane 1 has to
be set differently when SFP module is connected and when Topaz Switch
module is connected.

This is a temporary solution. When the comphy driver for armada-3720
will be added to the kernel, the comphy driver in u-boot shall also be
updated and this should be done differently then.

Signed-off-by: Marek Behun &lt;marek.behun@nic.cz&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>phy: marvell: a3700: Fix compatible string for ehci</title>
<updated>2018-05-14T08:01:56Z</updated>
<author>
<name>Marek Behún</name>
<email>marek.behun@nic.cz</email>
</author>
<published>2018-05-11T08:03:39Z</published>
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<id>urn:sha1:ca734a875dec089c3978663a0ce303d776365b20</id>
<content type='text'>
The DTS file for armada-37xx uses the string "marvell,armada3700-ehci",
but the code searched for "marvell,armada-3700-ehci".

Signed-off-by: Marek Behun &lt;marek.behun@nic.cz&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>phy: marvell: core: Cosmetic fixes</title>
<updated>2018-05-14T08:00:15Z</updated>
<author>
<name>Marek Behún</name>
<email>marek.behun@nic.cz</email>
</author>
<published>2018-04-24T15:21:28Z</published>
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<id>urn:sha1:2d7a0f4399f924422e959613b4c2634dcd0ad87e</id>
<content type='text'>
Move the reg_set* functions into comphy.h as static inline functions.
Change return type of get_*_string to const char *.

Signed-off-by: Marek Behun &lt;marek.behun@nic.cz&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>phy: marvell: a3700: Save/restore selector reg in SGMII init</title>
<updated>2018-05-14T08:00:15Z</updated>
<author>
<name>Marek Behún</name>
<email>marek.behun@nic.cz</email>
</author>
<published>2018-04-24T15:21:24Z</published>
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<id>urn:sha1:7288182aa6c11e4b0b2783cd4c7762f93f12cb64</id>
<content type='text'>
In SGMII initialization PIN_PIPE_SEL has to be zero when resetting
the PHY. Since comphy_mux already set the selector register to
correct values, we have to store it's value before setting it to 0
and restore it after SGMII init.

Signed-off-by: Marek Behun &lt;marek.behun@nic.cz&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>phy: marvell: a3700: Use comphy_mux on Armada 37xx.</title>
<updated>2018-05-14T08:00:15Z</updated>
<author>
<name>Marek Behún</name>
<email>marek.behun@nic.cz</email>
</author>
<published>2018-04-24T15:21:23Z</published>
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<id>urn:sha1:22f418935be4f5c6de26d2563a61d68136d80586</id>
<content type='text'>
Lane 0 supports SGMII1 and USB3.
Lane 1 supports SGMII0 and PEX0.
Lane 2 supports SATA0 and USB3.

This is needed for Armada 37xx.

This introduces new device tree bindings. AFAIK there is currently no
driver for Armada 37xx comphy in Linux. When such a driver will be
pushed into Linux, this will need to be rewritten accordingly.

Signed-off-by: Marek Behun &lt;marek.behun@nic.cz&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>phy: marvell: a3700: Fix SGMII cfg and stat register addresses</title>
<updated>2018-05-14T08:00:15Z</updated>
<author>
<name>Marek Behún</name>
<email>marek.behun@nic.cz</email>
</author>
<published>2018-04-24T15:21:22Z</published>
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<id>urn:sha1:3282a3e75fbea752f96df63baaad4c7f7d14d3b6</id>
<content type='text'>
The register addresses on lanes 0 and 1 are switched, first comes 1 and
then 0.

Signed-off-by: Marek Behun &lt;marek.behun@nic.cz&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>phy: marvell: mux: Support nontrivial node order in selector register</title>
<updated>2018-05-14T08:00:15Z</updated>
<author>
<name>Marek Behún</name>
<email>marek.behun@nic.cz</email>
</author>
<published>2018-04-24T15:21:21Z</published>
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<id>urn:sha1:7586ac2b49dd3046868354201ab6a208c3a5b82c</id>
<content type='text'>
Currently comphy_mux supports only trivial order of nodes in pin
selector register, that is lane N on position N*bitcount.

Add support for nontrivial order, with map stored in device tree
property mux-lane-order.

This is needed for Armada 37xx.

As far as I know, there is no driver for Armada 37xx comphy in the
kernel. When such a driver comes, this will need to be rewritten to
support the device tree bindings from the kernel.

Signed-off-by: Marek Behun &lt;marek.behun@nic.cz&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
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