u-boot.git/drivers/phy/marvell, branch v2022.01

phy: marvell: a3700: Return correct error code when power up fails

2021-10-08T06:33:52Z

Subroutines in comphy_usb2_power_up() and comphy_sgmii_power_up() functions may fail. In this case, do not continue execution of current function and instead jump to the end. Return value in 'ret' variable is already set. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese

phy: marvell: a3700: Fix configuring polarity invert bits

2021-10-08T06:33:52Z

phy_txd_inv or phy_rxd_inv needs to be set only in case when appropriate polarity is inverted. Otherwise these bits should be cleared. Same change was included in TF-A project: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/9406 Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese

phy: marvell: a3700: Set TXDCLK_2X_SEL bit during PCIe initialization

2021-10-08T06:33:52Z

Marvell Armada 3700 Functional Specifications, section 52.2 PCIe Link Initialization says that TXDCLK_2X_SEL bit needs to be enabled for PCIe Root Complex mode. Same change was included in TF-A project: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/9408 Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese

WS cleanup: remove trailing empty lines

2021-09-30T12:08:56Z

Signed-off-by: Wolfgang Denk

Merge tag 'v2021.10-rc5' into next

2021-09-27T13:45:36Z

Prepare v2021.10-rc5

phy: marvell: cp110: Support SATA invert polarity

2021-09-27T05:46:13Z

In commit b24bb99d cp110 configuration initially done in u-boot was removed and delegated to atf firmware as smc call. That commit didn't account for later introduced in d13b740c SATA invert polarity support. This patch adds support of passing SATA invert polarity flags to atf firmware during the smc call. Signed-off-by: Denis Odintsov Cc: Baruch Siach Cc: Rabeeh Khoury Cc: Stefan Roese Reviewed-by: Stefan Roese

Kconfig: Remove all default n/no options

2021-08-31T21:47:49Z

default n/no doesn't need to be specified. It is default option anyway. Signed-off-by: Michal Simek [trini: Rework FSP_USE_UPD portion] Signed-off-by: Tom Rini

phy: marvell: utmi: update utmi config which fixes usb2.0 instability

2021-04-29T05:45:24Z

- Add additional step which enables the Impedance and PLL calibration. - Enable old squelch detector instead of the new analog squelch detector circuit and update host disconnect threshold value. - Update LS TX driver strength coarse and fine adjustment values. Change-Id: Ifa0a585bfb5ecab0bfa033eed6874ff98b16a7df Signed-off-by: Grzegorz Jaszczyk

phy: marvell: add support for SFI1

2021-04-29T05:45:24Z

In CP115, comphy4 can be configured into SFI port1 (in addition to SFI0). This patch adds the option described above. In addition, rename all existing SFI/XFI references: COMPHY_TYPE_SFI --> COMPHY_TYPE_SFI0 No functional change for exsiting configuration. Change-Id: If9176222e0080424ba67347fe4d320215b1ba0c0 Signed-off-by: Igal Liberman Signed-off-by: Konstantin Porotchkin

phy: marvell: fix pll initialization for second utmi port

2021-04-29T05:45:24Z

According to Design Reference Specification the PHY PLL and Calibration register from PHY0 are shared for multi-port PHY. PLL control registers inside other PHY channels are not used. This commit reworks utmi device tree nodes in a way that common PHY PLL registers are moved to main utmi node. Accordingly both child nodes utmi-unit range is reduced and register offsets in utmi_phy.h are updated to this change. This fixes issues in scenarios when only utmi port1 was in use, which resulted with lack of correct pll initialization. Change-Id: Icc520dfa719f43a09493ab31f671efbe88872097 Signed-off-by: Grzegorz Jaszczyk