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<title>u-boot.git/drivers/phy/phy-zynqmp.c, branch master</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>phy: zynqmp: Only wait for PLL lock "primary" instances</title>
<updated>2026-01-12T12:01:27+00:00</updated>
<author>
<name>Sean Anderson</name>
<email>sean.anderson@linux.dev</email>
</author>
<published>2026-01-06T21:55:01+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=6f58580391d9457c0dc1a47bc2c9dd3fde7d8d4d'/>
<id>6f58580391d9457c0dc1a47bc2c9dd3fde7d8d4d</id>
<content type='text'>
For PCIe and DisplayPort, the phy instance represents the controller's
logical lane. Wait for the instance 0 phy's PLL to lock as other
instances will never lock. We do this in xpsgtr_wait_pll_lock so callers
don't have to determine the correct lane themselves.

The original comment is wrong about cumulative wait times. Since we are
just polling a bit, all subsequent waiters will finish immediately.

Signed-off-by: Sean Anderson &lt;sean.anderson@linux.dev&gt;
Link: https://lore.kernel.org/r/20240628205540.3098010-4-sean.anderson@linux.dev
Signed-off-by: Vinod Koul &lt;vkoul@kernel.org&gt;
[ Linux commit 235d8b663ab9e6cc13f8374abfffa559f50b57b6 ]
Link: https://lore.kernel.org/r/20260106215501.727524-5-sean.anderson@linux.dev
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
</content>
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<pre>
For PCIe and DisplayPort, the phy instance represents the controller's
logical lane. Wait for the instance 0 phy's PLL to lock as other
instances will never lock. We do this in xpsgtr_wait_pll_lock so callers
don't have to determine the correct lane themselves.

The original comment is wrong about cumulative wait times. Since we are
just polling a bit, all subsequent waiters will finish immediately.

Signed-off-by: Sean Anderson &lt;sean.anderson@linux.dev&gt;
Link: https://lore.kernel.org/r/20240628205540.3098010-4-sean.anderson@linux.dev
Signed-off-by: Vinod Koul &lt;vkoul@kernel.org&gt;
[ Linux commit 235d8b663ab9e6cc13f8374abfffa559f50b57b6 ]
Link: https://lore.kernel.org/r/20260106215501.727524-5-sean.anderson@linux.dev
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>phy: zynqmp: Store instance instead of type</title>
<updated>2026-01-12T12:01:27+00:00</updated>
<author>
<name>Sean Anderson</name>
<email>sean.anderson@linux.dev</email>
</author>
<published>2026-01-06T21:55:00+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7440a28528f4f8110f40c8dc6a3aa75b5306f1db'/>
<id>7440a28528f4f8110f40c8dc6a3aa75b5306f1db</id>
<content type='text'>
The phy "type" is just the combination of protocol and instance, and is
never used apart from that. Store the instance directly, instead of
converting to a type first. No functional change intended.

Signed-off-by: Sean Anderson &lt;sean.anderson@linux.dev&gt;
Link: https://lore.kernel.org/r/20240628205540.3098010-3-sean.anderson@linux.dev
Signed-off-by: Vinod Koul &lt;vkoul@kernel.org&gt;
[ Linux commit 6959d2367bc3503ac4ba3eb4ec6584a43150d6b3 ]
Link: https://lore.kernel.org/r/20260106215501.727524-4-sean.anderson@linux.dev
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
</content>
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<pre>
The phy "type" is just the combination of protocol and instance, and is
never used apart from that. Store the instance directly, instead of
converting to a type first. No functional change intended.

Signed-off-by: Sean Anderson &lt;sean.anderson@linux.dev&gt;
Link: https://lore.kernel.org/r/20240628205540.3098010-3-sean.anderson@linux.dev
Signed-off-by: Vinod Koul &lt;vkoul@kernel.org&gt;
[ Linux commit 6959d2367bc3503ac4ba3eb4ec6584a43150d6b3 ]
Link: https://lore.kernel.org/r/20260106215501.727524-4-sean.anderson@linux.dev
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>phy: zynqmp: Enable reference clock correctly</title>
<updated>2026-01-12T12:01:27+00:00</updated>
<author>
<name>Sean Anderson</name>
<email>sean.anderson@linux.dev</email>
</author>
<published>2026-01-06T21:54:59+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=8c3e514d66def2a0f20cdc1cfef4d58542444576'/>
<id>8c3e514d66def2a0f20cdc1cfef4d58542444576</id>
<content type='text'>
Lanes can use other lanes' reference clocks, as determined by refclk.
Use refclk to determine the clock to enable/disable instead of always
using the lane's own reference clock. This ensures the clock selected in
xpsgtr_configure_pll is the one enabled.

For the other half of the equation, always program REF_CLK_SEL even when
we are selecting the lane's own clock. This ensures that Linux's idea of
the reference clock matches the hardware. We use the "local" clock mux
for this instead of going through the ref clock network.

Signed-off-by: Sean Anderson &lt;sean.anderson@linux.dev&gt;
Link: https://lore.kernel.org/r/20240628205540.3098010-2-sean.anderson@linux.dev
Signed-off-by: Vinod Koul &lt;vkoul@kernel.org&gt;
[ Linux commit 687d6bccb28238fcfa65f7c1badfdfeac498c428 ]
Fixes: 1d78d683496 ("phy: zynqmp: Add serdes/psgtr driver")
Link: https://lore.kernel.org/r/20260106215501.727524-3-sean.anderson@linux.dev
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Lanes can use other lanes' reference clocks, as determined by refclk.
Use refclk to determine the clock to enable/disable instead of always
using the lane's own reference clock. This ensures the clock selected in
xpsgtr_configure_pll is the one enabled.

For the other half of the equation, always program REF_CLK_SEL even when
we are selecting the lane's own clock. This ensures that Linux's idea of
the reference clock matches the hardware. We use the "local" clock mux
for this instead of going through the ref clock network.

Signed-off-by: Sean Anderson &lt;sean.anderson@linux.dev&gt;
Link: https://lore.kernel.org/r/20240628205540.3098010-2-sean.anderson@linux.dev
Signed-off-by: Vinod Koul &lt;vkoul@kernel.org&gt;
[ Linux commit 687d6bccb28238fcfa65f7c1badfdfeac498c428 ]
Fixes: 1d78d683496 ("phy: zynqmp: Add serdes/psgtr driver")
Link: https://lore.kernel.org/r/20260106215501.727524-3-sean.anderson@linux.dev
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>phy: zynqmp: Allow variation in refclk rate</title>
<updated>2026-01-12T12:01:27+00:00</updated>
<author>
<name>Sean Anderson</name>
<email>sean.anderson@seco.com</email>
</author>
<published>2026-01-06T21:54:58+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0320459cbf857f4bc340d3a500a38a57218768d5'/>
<id>0320459cbf857f4bc340d3a500a38a57218768d5</id>
<content type='text'>
Due to limited available frequency ratios, the reference clock rate may
not be exactly the same as the required rate. Allow a small (100 ppm)
deviation.

Signed-off-by: Sean Anderson &lt;sean.anderson@seco.com&gt;
Link: https://lore.kernel.org/r/20230711194542.898230-1-sean.anderson@seco.com
Signed-off-by: Vinod Koul &lt;vkoul@kernel.org&gt;
[ Linux commit 76009ee76e05e30e29aade02e788aebe9ce9ffd2 ]
Link: https://lore.kernel.org/r/20260106215501.727524-2-sean.anderson@linux.dev
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Due to limited available frequency ratios, the reference clock rate may
not be exactly the same as the required rate. Allow a small (100 ppm)
deviation.

Signed-off-by: Sean Anderson &lt;sean.anderson@seco.com&gt;
Link: https://lore.kernel.org/r/20230711194542.898230-1-sean.anderson@seco.com
Signed-off-by: Vinod Koul &lt;vkoul@kernel.org&gt;
[ Linux commit 76009ee76e05e30e29aade02e788aebe9ce9ffd2 ]
Link: https://lore.kernel.org/r/20260106215501.727524-2-sean.anderson@linux.dev
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>phy: zynqmp: Fix sgmii clk ctrl GTR lane bit shift</title>
<updated>2025-06-02T07:13:48+00:00</updated>
<author>
<name>Frantisek Bohacek</name>
<email>rutherther@ditigal.xyz</email>
</author>
<published>2025-05-22T06:07:03+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=90df44fb4f0e1cbe18b02080ef8bf9e365f867b8'/>
<id>90df44fb4f0e1cbe18b02080ef8bf9e365f867b8</id>
<content type='text'>
The bitshift in GEM_CLK_CTRL register is five bits, not two. There are
four bits for each GEM, and one bit reserved in between.

This has caused that using more than one GEM is impossible,
additionally corrupting the GEM0's configuration, leaving GEM0
unusable as well (ie. if GEM0 and GEM1 are used, GEM1 configuration is
going to write to GEM0's registers wrong value, leaving GEM0 unusable)

Signed-off-by: Frantisek Bohacek &lt;rutherther@ditigal.xyz&gt;
Link: https://lore.kernel.org/r/20250522060703.4863-1-rutherther@ditigal.xyz
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The bitshift in GEM_CLK_CTRL register is five bits, not two. There are
four bits for each GEM, and one bit reserved in between.

This has caused that using more than one GEM is impossible,
additionally corrupting the GEM0's configuration, leaving GEM0
unusable as well (ie. if GEM0 and GEM1 are used, GEM1 configuration is
going to write to GEM0's registers wrong value, leaving GEM0 unusable)

Signed-off-by: Frantisek Bohacek &lt;rutherther@ditigal.xyz&gt;
Link: https://lore.kernel.org/r/20250522060703.4863-1-rutherther@ditigal.xyz
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"</title>
<updated>2024-05-20T19:35:03+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-05-20T19:35:03+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=03de305ec48b0bb28554372abb40ccd46dbe0bf9'/>
<id>03de305ec48b0bb28554372abb40ccd46dbe0bf9</id>
<content type='text'>
As part of bringing the master branch back in to next, we need to allow
for all of these changes to exist here.

Reported-by: Jonas Karlman &lt;jonas@kwiboo.se&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
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<pre>
As part of bringing the master branch back in to next, we need to allow
for all of these changes to exist here.

Reported-by: Jonas Karlman &lt;jonas@kwiboo.se&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""</title>
<updated>2024-05-19T14:16:36+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-05-19T02:20:43+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d678a59d2d719da9e807495b4b021501f2836ca5'/>
<id>d678a59d2d719da9e807495b4b021501f2836ca5</id>
<content type='text'>
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay
Ethernet"' I failed to notice that b4 noticed it was based on next and
so took that as the base commit and merged that part of next to master.

This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing
changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35.

Reported-by: Jonas Karlman &lt;jonas@kwiboo.se&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
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<pre>
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay
Ethernet"' I failed to notice that b4 noticed it was based on next and
so took that as the base commit and merged that part of next to master.

This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing
changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35.

Reported-by: Jonas Karlman &lt;jonas@kwiboo.se&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>phy: Remove &lt;common.h&gt; and add needed includes</title>
<updated>2024-05-07T14:00:56+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-05-02T01:31:07+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5323767510b78bfa8c79300da3e512c93d965aa6'/>
<id>5323767510b78bfa8c79300da3e512c93d965aa6</id>
<content type='text'>
Remove &lt;common.h&gt; from this driver directory and when needed
add missing include files directly.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Remove &lt;common.h&gt; from this driver directory and when needed
add missing include files directly.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>phy: zynqmp: Increase timeout value to 10ms</title>
<updated>2022-05-18T11:17:54+00:00</updated>
<author>
<name>Ashok Reddy Soma</name>
<email>ashok.reddy.soma@xilinx.com</email>
</author>
<published>2022-05-10T13:12:34+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e9869f474c35b81577066441dce6960c03089023'/>
<id>e9869f474c35b81577066441dce6960c03089023</id>
<content type='text'>
Observing psgtr pll timeouts with some usb hubs and devices behind it.
Increase timeout to 10ms to take care of it.

Signed-off-by: Ashok Reddy Soma &lt;ashok.reddy.soma@xilinx.com&gt;
Link: https://lore.kernel.org/r/20220510131234.2650-1-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Observing psgtr pll timeouts with some usb hubs and devices behind it.
Increase timeout to 10ms to take care of it.

Signed-off-by: Ashok Reddy Soma &lt;ashok.reddy.soma@xilinx.com&gt;
Link: https://lore.kernel.org/r/20220510131234.2650-1-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>phy: zynqmp: Add support for sata and DP phy initialization</title>
<updated>2022-02-15T12:04:28+00:00</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@xilinx.com</email>
</author>
<published>2022-02-07T09:36:32+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=462f76bc002da9c1d0f4b27380a493dc7928df7e'/>
<id>462f76bc002da9c1d0f4b27380a493dc7928df7e</id>
<content type='text'>
DP is untested but just c&amp;p from Linux driver. Sata is tested on kv260-revA
board which has SATA connector populated.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Link: https://lore.kernel.org/r/d231610160e76a2ad1b4a163e0e8db0ddc4733e2.1644226590.git.michal.simek@xilinx.com
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
DP is untested but just c&amp;p from Linux driver. Sata is tested on kv260-revA
board which has SATA connector populated.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Link: https://lore.kernel.org/r/d231610160e76a2ad1b4a163e0e8db0ddc4733e2.1644226590.git.michal.simek@xilinx.com
</pre>
</div>
</content>
</entry>
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