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<title>u-boot.git/drivers/phy/rockchip/Makefile, branch master</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>phy: rockchip: Add Rockchip INNO HDMI PHY driver</title>
<updated>2024-04-21T07:07:00+00:00</updated>
<author>
<name>Jagan Teki</name>
<email>jagan@edgeble.ai</email>
</author>
<published>2024-01-17T07:51:48+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=aa22711846036b4fb8b30da560a1ea5f90d50551'/>
<id>aa22711846036b4fb8b30da560a1ea5f90d50551</id>
<content type='text'>
Add Rockchip INNO HDMI PHY driver for RK3328.

Reference from linux-next phy-rockchip-inno-hdmi driver.

Signed-off-by: Jagan Teki &lt;jagan@edgeble.ai&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add Rockchip INNO HDMI PHY driver for RK3328.

Reference from linux-next phy-rockchip-inno-hdmi driver.

Signed-off-by: Jagan Teki &lt;jagan@edgeble.ai&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>phy: rockchip: add usbdp combo phy driver</title>
<updated>2023-07-28T10:45:02+00:00</updated>
<author>
<name>Frank Wang</name>
<email>frank.wang@rock-chips.com</email>
</author>
<published>2023-05-29T10:01:33+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7b57ca18f8a3a88216b69cd295e1eed2b0c6c1be'/>
<id>7b57ca18f8a3a88216b69cd295e1eed2b0c6c1be</id>
<content type='text'>
This adds a new USBDP combo PHY with Samsung IP block driver.
The PHY is a combo between USB 3.0 and DisplayPort alt mode.

Signed-off-by: Frank Wang &lt;frank.wang@rock-chips.com&gt;
[eugen.hristev@collabora.com: ported to 2023.07, clean-up]
Signed-off-by: Eugen Hristev &lt;eugen.hristev@collabora.com&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This adds a new USBDP combo PHY with Samsung IP block driver.
The PHY is a combo between USB 3.0 and DisplayPort alt mode.

Signed-off-by: Frank Wang &lt;frank.wang@rock-chips.com&gt;
[eugen.hristev@collabora.com: ported to 2023.07, clean-up]
Signed-off-by: Eugen Hristev &lt;eugen.hristev@collabora.com&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drivers: phy: add Innosilicon DSI-DPHY driver</title>
<updated>2023-04-21T07:16:01+00:00</updated>
<author>
<name>Chris Morgan</name>
<email>macromorgan@hotmail.com</email>
</author>
<published>2023-03-24T18:53:06+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=bf57dd5889beae9ff871a657f43ed72345ab2e6c'/>
<id>bf57dd5889beae9ff871a657f43ed72345ab2e6c</id>
<content type='text'>
Add support for the Innosilicon DSI-DPHY driver for Rockchip SOCs.
The driver was ported from Linux and tested on a Rockchip RK3566
based device to query the panel ID via a DSI command.

Signed-off-by: Chris Morgan &lt;macromorgan@hotmail.com&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add support for the Innosilicon DSI-DPHY driver for Rockchip SOCs.
The driver was ported from Linux and tested on a Rockchip RK3566
based device to query the panel ID via a DSI command.

Signed-off-by: Chris Morgan &lt;macromorgan@hotmail.com&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drivers: phy: add naneng combphy for rk3568</title>
<updated>2023-02-28T10:07:27+00:00</updated>
<author>
<name>Jagan Teki</name>
<email>jagan@edgeble.ai</email>
</author>
<published>2023-02-17T11:58:41+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=82220526ac9887c39d2d5caa567a20378b3122b7'/>
<id>82220526ac9887c39d2d5caa567a20378b3122b7</id>
<content type='text'>
RK3568 has three combo phys, and PCIe/USB3/SATA/QSGMII controllers
share one pipe interface for each combo phy, here is the diagram
of the complex connection.

+----------------+
|                |     +------+
| USB3 OTG CTRL0 |----&gt;|      |
|                |     |      |     +------------+
+----------------+     | PIPE |     |            |
                       | MUX  |----&gt;| Combo PHY0 |
+----------------+     |      |     |            |
|                |     |      |     +------------+
|   SATA CTRL0   |----&gt;|      |
|                |     +------+
+----------------+

+----------------+
|                |     +------+
| USB3 HOST CTRL1|----&gt;|      |
|                |     |      |     +------------+
+----------------+     | PIPE |     |            |
                       | MUX  |----&gt;| Combo PHY1 |
+----------------+     |      |     |            |
|                |----&gt;|      |     +------------+
|   SATA CTRL1   |  --&gt;|      |
|                |  |  +------+
+----------------+  |
                    |
+----------------+  |
|                |  |  +------+
|  QSGMII CTRL   |----&gt;|      |
|                |     |      |     +------------+
+----------------+     | PIPE |     |            |
                       | MUX  |----&gt;| Combo PHY2 |
+----------------+     |      |     |            |
|                |----&gt;|      |     +------------+
|   SATA CTRL2   |  --&gt;|      |
|                |  |  +------+
+----------------+  |
                    |
+----------------+  |
|                |  |
|  PCIe2 1-Lane  |---
|                |
+----------------+

Co-developed-by: Manoj Sai &lt;abbaraju.manojsai@amarulasolutions.com&gt;
Signed-off-by: Manoj Sai &lt;abbaraju.manojsai@amarulasolutions.com&gt;
Co-developed-by: Yifeng Zhao &lt;yifeng.zhao@rock-chips.com&gt;
Signed-off-by: Yifeng Zhao &lt;yifeng.zhao@rock-chips.com&gt;
Signed-off-by: Jagan Teki &lt;jagan@edgeble.ai&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
RK3568 has three combo phys, and PCIe/USB3/SATA/QSGMII controllers
share one pipe interface for each combo phy, here is the diagram
of the complex connection.

+----------------+
|                |     +------+
| USB3 OTG CTRL0 |----&gt;|      |
|                |     |      |     +------------+
+----------------+     | PIPE |     |            |
                       | MUX  |----&gt;| Combo PHY0 |
+----------------+     |      |     |            |
|                |     |      |     +------------+
|   SATA CTRL0   |----&gt;|      |
|                |     +------+
+----------------+

+----------------+
|                |     +------+
| USB3 HOST CTRL1|----&gt;|      |
|                |     |      |     +------------+
+----------------+     | PIPE |     |            |
                       | MUX  |----&gt;| Combo PHY1 |
+----------------+     |      |     |            |
|                |----&gt;|      |     +------------+
|   SATA CTRL1   |  --&gt;|      |
|                |  |  +------+
+----------------+  |
                    |
+----------------+  |
|                |  |  +------+
|  QSGMII CTRL   |----&gt;|      |
|                |     |      |     +------------+
+----------------+     | PIPE |     |            |
                       | MUX  |----&gt;| Combo PHY2 |
+----------------+     |      |     |            |
|                |----&gt;|      |     +------------+
|   SATA CTRL2   |  --&gt;|      |
|                |  |  +------+
+----------------+  |
                    |
+----------------+  |
|                |  |
|  PCIe2 1-Lane  |---
|                |
+----------------+

Co-developed-by: Manoj Sai &lt;abbaraju.manojsai@amarulasolutions.com&gt;
Signed-off-by: Manoj Sai &lt;abbaraju.manojsai@amarulasolutions.com&gt;
Co-developed-by: Yifeng Zhao &lt;yifeng.zhao@rock-chips.com&gt;
Signed-off-by: Yifeng Zhao &lt;yifeng.zhao@rock-chips.com&gt;
Signed-off-by: Jagan Teki &lt;jagan@edgeble.ai&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>phy: rockchip: Add Rockchip Synopsys PCIe 3.0 PHY</title>
<updated>2021-01-21T04:00:45+00:00</updated>
<author>
<name>Shawn Lin</name>
<email>shawn.lin@rock-chips.com</email>
</author>
<published>2021-01-15T10:01:21+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=6ec62b6ca6986196d733383e628e7f5618f4cdd1'/>
<id>6ec62b6ca6986196d733383e628e7f5618f4cdd1</id>
<content type='text'>
Add the Rockchip Synopsys based PCIe 3.0 PHY driver as
part of Generic PHY framework.

Signed-off-by: Shawn Lin &lt;shawn.lin@rock-chips.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Kever Yang&lt;kever.yang@rock-chips.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add the Rockchip Synopsys based PCIe 3.0 PHY driver as
part of Generic PHY framework.

Signed-off-by: Shawn Lin &lt;shawn.lin@rock-chips.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Kever Yang&lt;kever.yang@rock-chips.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>phy: Add Rockchip PCIe PHY driver</title>
<updated>2020-07-22T12:22:42+00:00</updated>
<author>
<name>Jagan Teki</name>
<email>jagan@amarulasolutions.com</email>
</author>
<published>2020-07-09T18:11:01+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7bdeb4ef4ca24d5b4b5c4c62eb8b32a5f1d8249d'/>
<id>7bdeb4ef4ca24d5b4b5c4c62eb8b32a5f1d8249d</id>
<content type='text'>
Add the Rockchip PCIe PHY driver as part of
Generic PHY framework.

Signed-off-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add the Rockchip PCIe PHY driver as part of
Generic PHY framework.

Signed-off-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>phy: rockchip: Add Rockchip USB TypeC PHY driver</title>
<updated>2020-05-29T10:13:19+00:00</updated>
<author>
<name>Jagan Teki</name>
<email>jagan@amarulasolutions.com</email>
</author>
<published>2020-05-26T03:33:45+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=214de08767a7d83df7a6a93d50b263d3cc714acf'/>
<id>214de08767a7d83df7a6a93d50b263d3cc714acf</id>
<content type='text'>
Add USB TYPEC PHY driver for rockchip platform.

Referenced from Linux TypeC PHY driver, currently
supporting usb3-port and dp-port need to add it
in the future.

Signed-off-by: Frank Wang &lt;frank.wang@rock-chips.com&gt;
Signed-off-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add USB TYPEC PHY driver for rockchip platform.

Referenced from Linux TypeC PHY driver, currently
supporting usb3-port and dp-port need to add it
in the future.

Signed-off-by: Frank Wang &lt;frank.wang@rock-chips.com&gt;
Signed-off-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>phy: rockchip: Add Rockchip USB2PHY driver</title>
<updated>2020-05-29T10:13:19+00:00</updated>
<author>
<name>Jagan Teki</name>
<email>jagan@amarulasolutions.com</email>
</author>
<published>2020-05-26T03:33:44+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ac97a9ece14e930b0856b13d1d13d6b40763258e'/>
<id>ac97a9ece14e930b0856b13d1d13d6b40763258e</id>
<content type='text'>
Add Rockchip USB2PHY driver with initial support.

This will help to use it for EHCI controller in host
mode, and USB 3.0 controller in otg mode.

More functionality like charge, vbus detection will
add it in future changes.

Signed-off-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
Signed-off-by: Frank Wang &lt;frank.wang@rock-chips.com&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add Rockchip USB2PHY driver with initial support.

This will help to use it for EHCI controller in host
mode, and USB 3.0 controller in otg mode.

More functionality like charge, vbus detection will
add it in future changes.

Signed-off-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
Signed-off-by: Frank Wang &lt;frank.wang@rock-chips.com&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</pre>
</div>
</content>
</entry>
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