u-boot.git/drivers/phy/rockchip, branch v2023.04

drivers: phy: add naneng combphy for rk3568

2023-02-28T10:07:27Z

RK3568 has three combo phys, and PCIe/USB3/SATA/QSGMII controllers share one pipe interface for each combo phy, here is the diagram of the complex connection. +----------------+ | | +------+ | USB3 OTG CTRL0 |---->| | | | | | +------------+ +----------------+ | PIPE | | | | MUX |---->| Combo PHY0 | +----------------+ | | | | | | | | +------------+ | SATA CTRL0 |---->| | | | +------+ +----------------+ +----------------+ | | +------+ | USB3 HOST CTRL1|---->| | | | | | +------------+ +----------------+ | PIPE | | | | MUX |---->| Combo PHY1 | +----------------+ | | | | | |---->| | +------------+ | SATA CTRL1 | -->| | | | | +------+ +----------------+ | | +----------------+ | | | | +------+ | QSGMII CTRL |---->| | | | | | +------------+ +----------------+ | PIPE | | | | MUX |---->| Combo PHY2 | +----------------+ | | | | | |---->| | +------------+ | SATA CTRL2 | -->| | | | | +------+ +----------------+ | | +----------------+ | | | | | PCIe2 1-Lane |--- | | +----------------+ Co-developed-by: Manoj Sai Signed-off-by: Manoj Sai Co-developed-by: Yifeng Zhao Signed-off-by: Yifeng Zhao Signed-off-by: Jagan Teki Reviewed-by: Kever Yang

phy: rockchip-inno-usb2: Add USB2 PHY for rk3568

2023-02-28T10:07:27Z

RK3568 has two USB 2.0 PHYs, and each PHY has two ports, the OTG port of PHY0 support OTG mode with charging detection function, they are similar to previous Rockchip SoCs. However, there are three different designs for RK3568 USB 2.0 PHY. 1. RK3568 uses independent USB GRF module for each USB 2.0 PHY. 2. RK3568 accesses the registers of USB 2.0 PHY IP directly by APB. 3. The two ports of USB 2.0 PHY share one interrupt. This patch only PHY1 with necessary attributes required to function USBPHY1 on U-Boot. Co-developed-by: Ren Jianing Signed-off-by: Ren Jianing Co-developed-by: Jagan Teki Signed-off-by: Jagan Teki Signed-off-by: Manoj Sai Reviewed-by: Kever Yang

phy: rockchip: inno-usb2: Add support #address_cells = 2

2023-02-28T10:07:27Z

New Rockchip devices have the usb phy nodes as standalone devices. These nodes have register nodes with #address_cells = 2, but only use 32 bit addresses. Adjust the driver to check if the returned address is "0", and adjust the index in that case. Derived and adjusted the similar change from linux-next with below commit <9c19c531dc98> ("phy: phy-rockchip-inno-usb2: support #address_cells = 2") Co-developed-by: Manoj Sai Signed-off-by: Manoj Sai Signed-off-by: Jagan Teki Reviewed-by: Kever Yang

phy: rockchip: handle clock without enable function

2022-12-19T02:56:12Z

If a clock doesn't supply the enable hook, clk_enable() will return -ENOSYS. In this case the clock is always enabled so there is no error and the phy initialisation should continue. Signed-off-by: John Keeping Reviewed-by: Kever Yang

common: Drop asm/global_data.h from common header

2021-02-02T20:33:42Z

Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include at all, so remove that include. Signed-off-by: Simon Glass Signed-off-by: Tom Rini

pci: Add Rockchip dwc based PCIe controller driver

2021-01-21T04:00:45Z

Add Rockchip dwc based PCIe controller driver for rk356x platform. Driver support Gen3 by operating as a Root complex. Signed-off-by: Shawn Lin Reviewed-by: Simon Glass Reviewed-by: Kever Yang

phy: rockchip: Add Rockchip Synopsys PCIe 3.0 PHY

2021-01-21T04:00:45Z

Add the Rockchip Synopsys based PCIe 3.0 PHY driver as part of Generic PHY framework. Signed-off-by: Shawn Lin Reviewed-by: Simon Glass Reviewed-by: Kever Yang

dm: treewide: Rename auto_alloc_size members to be shorter

2020-12-13T15:00:25Z

This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass

phy: rockchip: Fix not calling dev_err with a device

2020-09-30T12:53:29Z

Get the device from phy, or pass the phy in. Signed-off-by: Sean Anderson Reviewed-by: Kever Yang Tested-by: Patrick Delaunay

phy: Add Rockchip PCIe PHY driver

2020-07-22T12:22:42Z

Add the Rockchip PCIe PHY driver as part of Generic PHY framework. Signed-off-by: Jagan Teki Reviewed-by: Kever Yang