u-boot.git/drivers/phy/rockchip, branch v2024.01

phy: rockchip: naneng-combphy: Use signal from comb PHY on RK3588

2023-10-07T02:23:12Z

Route signal from comb PHY instead of PCIe3 PHY to PCIe1l0 and PCIe1l1. Fixes use of pcie2x1l0 on ROCK 5B. Code imported from mainline linux driver. Fixes: c5b4a012bca8 ("phy: rockchip: naneng-combphy: Support rk3588") Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang

phy: rockchip: snps-pcie3: Add support for RK3588

2023-10-07T02:23:12Z

Add support for the RK3588 variant to the driver. Code imported almost 1:1 from mainline linux driver. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang

phy: rockchip: snps-pcie3: Add bifurcation support for RK3568

2023-10-07T02:23:12Z

Configure aggregation or bifurcation mode on RK3568 based on the value of data-lanes property. Code imported almost 1:1 from mainline linux driver. Fixes: 6ec62b6ca698 ("phy: rockchip: Add Rockchip Synopsys PCIe 3.0 PHY") Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang

phy: rockchip: snps-pcie3: Refactor to use a phy_init ops

2023-10-07T02:23:12Z

Add a phy_init ops in preparation for upcoming support of a RK3588 variant in the driver. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang

phy: rockchip: snps-pcie3: Refactor to use clk_bulk API

2023-10-07T02:23:12Z

Change to use clk_bulk API and syscon_regmap_lookup_by_phandle to simplify in preparation for upcoming support of a RK3588 variant. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang

phy: rockchip-inno-usb2: Add USB2 PHY for RK3328

2023-07-31T12:33:18Z

USB2.0 Host and OTG controllers in RK3328 are using USB2PHY. Add support for it. Signed-off-by: Jagan Teki Reviewed-by: Xavier Drudis Ferran Reviewed-by: Kever Yang

phy: rockchip: add usbdp combo phy driver

2023-07-28T10:45:02Z

This adds a new USBDP combo PHY with Samsung IP block driver. The PHY is a combo between USB 3.0 and DisplayPort alt mode. Signed-off-by: Frank Wang [eugen.hristev@collabora.com: ported to 2023.07, clean-up] Signed-off-by: Eugen Hristev Reviewed-by: Kever Yang

phy: rockchip: inno-usb2: fix phy reg=0 case

2023-06-29T10:31:48Z

The support for #address-cells=2 has a loophole: if the reg is actually 0, but the #address-cells is actually 1, like in such case below: syscon { #address-cells = <1>; phy { reg = <0 0x10>; }; }; then the second u32 of the 'reg' is the size, not the address. The code should check for the parent's #address-cells value, and not assume that if the first u32 is 0, then the #address-cells is 2, and the reg property is something like reg = <0 0xff00 0x10>; Fixed this by looking for the #address-cells value and retrieving the reg address only if this is ==2. To avoid breaking anything I also kept the check `if reg==0` as some DT's may have a wrong #address-cells as parent and even if this commit is correct, it might break the existing wrong device-trees. Fixes: d538efb9adcf ("phy: rockchip: inno-usb2: Add support #address_cells = 2") Signed-off-by: Eugen Hristev Reviewed-by: Kever Yang

phy: rockchip-inno-usb2: Implement clock operations for usb2phy clock

2023-06-07T21:41:47Z

This clock doesn't seem needed but appears in a phandle list used by ehci-generic.c to bulk enable it. The phandle list comes from linux, where it is needed for suspend/resume to work [1]. My tests give the same results with or without this patch, but Marek Vasut found it weird to declare an empty clk_ops [2]. So I adapted the code from linux 6.1-rc8 so that it hopefully works if it ever has some user. For now, without real use, it seems to at least not give any errors when called. Link: [1] https://lkml.kernel.org/lkml/1731551.Q6cHK6n5ZM@phil/T/ [2] https://patchwork.ozlabs.org/project/uboot/patch/Y5IWpjYLB4aXMy9o@localhost/ Cc: Simon Glass Cc: Philipp Tomsich Cc: Kever Yang Cc: Lukasz Majewski Cc: Sean Anderson Cc: Marek Vasut Cc: Christoph Fritz Cc: Jagan Teki Signed-off-by: Xavier Drudis Ferran Reviewed-by: Kever Yang Reviewed-by: Jagan Teki Tested-by: Jagan Teki # rk3399, rk3328, rv1126

phy: rockchip-inno-usb2: Add usb2phy clock provider of 480MHz clock

2023-06-07T21:41:47Z

arch/arm/dts/rk3399.dtsi has a node usb_host0_ehci: usb@fe380000 { compatible = "generic-ehci"; with clocks: clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, <&u2phy0>; The first 2 refer to nodes with class UCLASS_CLK, but &u2phy0 has class UCLASS_PHY. u2phy0: usb2phy@e450 { compatible = "rockchip,rk3399-usb2phy"; Since clk_get_bulk() only looks for devices with UCLASS_CLK, it fails with -ENODEV and then ehci_usb_probe() aborts. The consequence is peripherals connected to a USB 2 port (e.g. in a Rock Pi 4 the white port, nearer the edge) not being detected. They're detected if CONFIG_USB_OHCI_GENERIC is selected in Kconfig, because ohci_usb_probe() does not abort when one clk_get_by_index() fails, but then they work in USB 1 mode. rk3399.dtsi comes from linux and the u2phy0 was added[1] to the clock list in: commit b5d1c57299734f5b54035ef2e61706b83041f20c Author: William wu Date: Wed Dec 21 18:41:05 2016 +0800 arm64: dts: rockchip: add u2phy clock for ehci and ohci of rk3399 We found that the suspend process was blocked when it run into ehci/ohci module due to clk-480m of usb2-phy was disabled. [...] Suspend concerns don't apply to U-Boot, and the problem with U-Boot failing to probe EHCI doesn't apply to linux, because in linux rockchip_usb2phy_clk480m_register makes u2phy0 a proper clock provider when called by rockchip_usb2phy_probe(). So I can think of a few alternative solutions: 1- Change ehci_usb_probe() to make it more similar to ohci_usb_probe(), and survive failure to get one clock. Looks a little harder, and I don't know whether it could break something if it ignored a clock that was important for something else than suspend. 2- Change rk3399.dtsi effectively reverting the linux commit b5d1c57299734f5b54035ef2e61706b83041f20c. This dealigns the .dtsi from linux and seems fragile at the next synchronisation. 3- Change the clock list in rk3399-u-boot.dtsi or somewhere else. This survives .dts* sync but may survive "too much" and miss some change from linux that we might want. 4- Enable CONFIG_USB_OHCI_GENERIC and use the ports in USB 1 mode. This would need to be made for all boards using rk3399. In a simple test reading one file from USB storage it gave 769.5 KiB/s instead of 20.5 MiB/s with solution 2. 5- Trying to replicate linux and have usb2phy somehow provide a clk, or have a separate clock device for usb2phy in addition to the phy device. This patch tries to implement option 5 as Marek Vasut requested in December 5th. Options 1 and 3 didn't get through [2][3]. It just registers usb2phy as a clock driver (device_bind_driver() didn't work but device_bind_driver_to_node() did), without any specific operations, so that ehci-generic.c finds it and is happy. It worked in my tests on a Rock Pi 4 B+ (rk3399). Link: [1] https://lkml.kernel.org/lkml/1731551.Q6cHK6n5ZM@phil/T/ [2] https://patchwork.ozlabs.org/project/uboot/patch/20220701185959.GC1700@begut/ [3] https://patchwork.ozlabs.org/project/uboot/patch/Y44+ayJfUlI08ptM@localhost/ Cc: Simon Glass Cc: Philipp Tomsich Cc: Kever Yang Cc: Lukasz Majewski Cc: Sean Anderson Cc: Marek Vasut Cc: Christoph Fritz Cc: Jagan Teki Signed-off-by: Xavier Drudis Ferran Reviewed-by: Kever Yang Reviewed-by: Jagan Teki Tested-by: Jagan Teki # rk3399, rk3328, rv1126