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<title>u-boot.git/drivers/phy/ti/Kconfig, branch master</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/phy/ti/Kconfig?h=master</id>
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<updated>2026-06-03T14:55:55Z</updated>
<entry>
<title>phy: Kconfig: use bool instead of tristate</title>
<updated>2026-06-03T14:55:55Z</updated>
<author>
<name>David Lechner</name>
<email>dlechner@baylibre.com</email>
</author>
<published>2026-05-13T14:11:52Z</published>
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<id>urn:sha1:3518bf17ba4435067bd5c7b3eb7148e7182fe6b1</id>
<content type='text'>
Change all uses of tristate in the PHY Kconfigs to bool. U-Boot does
not support modules, so tristate does not make sense here.

Signed-off-by: David Lechner &lt;dlechner@baylibre.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
Reviewed-by: Quentin Schulz &lt;quentin.schulz@cherry.de&gt;
Reviewed-by: Macpaul Lin &lt;macpaul.lin@mediatek.com&gt;
Reviewed-by: Anshul Dalal &lt;anshuld@ti.com&gt;
Reviewed-by: Casey Connolly &lt;casey.connolly@linaro.org&gt;
</content>
</entry>
<entry>
<title>phy: ti: Add config to enable J721E WIZ SERDES wrapper at SPL stage</title>
<updated>2026-03-16T14:24:04Z</updated>
<author>
<name>Hrushikesh Salunke</name>
<email>h-salunke@ti.com</email>
</author>
<published>2026-02-16T10:28:31Z</published>
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<id>urn:sha1:35e1083fb930ba1fa3a3c5cd139bf8285043c191</id>
<content type='text'>
Add SPL_PHY_J721E_WIZ configuration option to enable the WIZ SERDES
wrapper driver in SPL stage. This is required for PCIe boot support
where SERDES configuration must be done early in the boot sequence
before loading the bootloader image over PCIe.

Signed-off-by: Hrushikesh Salunke &lt;h-salunke@ti.com&gt;
Signed-off-by: Siddharth Vadapalli &lt;s-vadapalli@ti.com&gt;
</content>
</entry>
<entry>
<title>phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC</title>
<updated>2021-07-27T05:27:12Z</updated>
<author>
<name>Jean-Jacques Hiblot</name>
<email>jjhiblot@ti.com</email>
</author>
<published>2021-07-21T15:58:38Z</published>
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<id>urn:sha1:1a83f9931e052168c225033d9c642112142dab70</id>
<content type='text'>
Add support for WIZ module present in TI's J721E SoC. WIZ is a SERDES
wrapper used to configure some of the input signals to the SERDES. It is
used with both Sierra(16G) and Torrent(10G) SERDES. This driver configures
three clock selects (pll0, pll1, dig) and supports resets for each of the
lanes.

This is an adaptation of the linux driver.

Signed-off-by: Jean-Jacques Hiblot &lt;jjhiblot@ti.com&gt;
Signed-off-by: Vignesh Raghavendra &lt;vigneshr@ti.com&gt;
Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
Signed-off-by: Lokesh Vutla &lt;lokeshvutla@ti.com&gt;
Link: https://lore.kernel.org/r/20210721155849.20994-10-kishon@ti.com
</content>
</entry>
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