u-boot.git/drivers/phy/ti, branch v2023.04

phy: ti: j721e-wiz: add j784s4-wiz-10g module support

2022-10-18T13:48:22Z

Add support for j784s4-wiz-10g device which has two core reference clocks (e.g core_ref_clk, core_ref1_clk) which requires an additional mux selection option. Signed-off-by: Matt Ranostay

phy: ti: j721e-wiz: use OF data for device specific data

2022-07-25T13:38:47Z

Move device specific data into OF data structure so it is easier to maintain and we can get rid of if statements. Based on: https://lore.kernel.org/linux-phy/20220526064121.27625-1-rogerq@kernel.org/T/#u Cc: Roger Quadros Signed-off-by: Matt Ranostay

phy: ti: phy-j721e-wiz.c: Fix the condition for setting P_ENABLE_FORCE

2022-02-08T16:00:03Z

Fix the condition for setting P_ENABLE_FORCE bit, by syncing with the driver in kernel. Signed-off-by: Aswath Govindraju

phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC

2021-07-27T05:27:12Z

Add support for WIZ module present in TI's J721E SoC. WIZ is a SERDES wrapper used to configure some of the input signals to the SERDES. It is used with both Sierra(16G) and Torrent(10G) SERDES. This driver configures three clock selects (pll0, pll1, dig) and supports resets for each of the lanes. This is an adaptation of the linux driver. Signed-off-by: Jean-Jacques Hiblot Signed-off-by: Vignesh Raghavendra Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Lokesh Vutla Link: https://lore.kernel.org/r/20210721155849.20994-10-kishon@ti.com