u-boot.git/drivers/phy/ti, branch v2024.04

tree-wide: Replace http:// link with https:// link for ti.com

2023-11-10T16:01:50Z

Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon

phy: ti: j721e-wiz: Add SGMII support in WIZ driver for J721E

2023-08-15T21:46:39Z

Enable full rate divider configuration support for J721E_WIZ_16G for SGMII. Signed-off-by: Siddharth Vadapalli

phy: ti: phy-j721e-wiz: Add SGMII support in wiz driver for J7200

2023-08-15T21:46:39Z

Select the same mac divider for SGMII too as the one being used for QSGMII. Enable full rate divider configuration support for J721E_WIZ_10G for SGMII. Signed-off-by: Siddharth Vadapalli

phy: ti: phy-j721e-wiz: Add j721s2-wiz-10g module support

2023-06-01T16:40:16Z

Add support for j721s2-wiz-10g device to use clock-names interface instead of explicitly defining clock nodes within device tree node. Signed-off-by: Ravi Gunasekaran

phy: ti: j721e-wiz: Add support to enable LN23 Type-C swap

2023-03-29T17:30:29Z

The WIZ acts as a wrapper for SerDes and has Lanes 0 and 2 reserved for USB for type-C lane swap if Lane 1 and Lane 3 are linked to the USB PHY that is integrated into the SerDes IP. The WIZ control register has to be configured to support this lane swap feature. The support for swapping lanes 2 and 3 is missing and therefore add support to configure the control register to swap between lanes 2 and 3 if PHY type is USB. Signed-off-by: Sinthu Raja

phy: ti: j721e-wiz: Manage TypeC lane swap if typec-dir-gpios not specified

2023-03-29T17:30:29Z

It's possible that the Type-C plug orientation on the DIR line will be implemented through hardware design. In that situation, there won't be an external GPIO line available, but the driver still needs to address this since the DT won't use the typec-dir-gpios property. Add code to handle LN10 Type-C swap if typec-dir-gpios property is not specified in DT. Signed-off-by: Sinthu Raja

phy: ti: j721e-wiz: add j784s4-wiz-10g module support

2022-10-18T13:48:22Z

Add support for j784s4-wiz-10g device which has two core reference clocks (e.g core_ref_clk, core_ref1_clk) which requires an additional mux selection option. Signed-off-by: Matt Ranostay

phy: ti: j721e-wiz: use OF data for device specific data

2022-07-25T13:38:47Z

Move device specific data into OF data structure so it is easier to maintain and we can get rid of if statements. Based on: https://lore.kernel.org/linux-phy/20220526064121.27625-1-rogerq@kernel.org/T/#u Cc: Roger Quadros Signed-off-by: Matt Ranostay

phy: ti: phy-j721e-wiz.c: Fix the condition for setting P_ENABLE_FORCE

2022-02-08T16:00:03Z

Fix the condition for setting P_ENABLE_FORCE bit, by syncing with the driver in kernel. Signed-off-by: Aswath Govindraju

phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC

2021-07-27T05:27:12Z

Add support for WIZ module present in TI's J721E SoC. WIZ is a SERDES wrapper used to configure some of the input signals to the SERDES. It is used with both Sierra(16G) and Torrent(10G) SERDES. This driver configures three clock selects (pll0, pll1, dig) and supports resets for each of the lanes. This is an adaptation of the linux driver. Signed-off-by: Jean-Jacques Hiblot Signed-off-by: Vignesh Raghavendra Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Lokesh Vutla Link: https://lore.kernel.org/r/20210721155849.20994-10-kishon@ti.com