u-boot.git/drivers/phy, branch next Unnamed repository; edit this file 'description' to name the repository. Merge patch series "Add PCIe Boot support for TI J784S4 SoC" 2026-03-16T14:24:18+00:00 Tom Rini trini@konsulko.com 2026-03-16T14:24:18+00:00 841856ed9675b26ec517fdd00b5cc0aef8db508e Siddharth Vadapalli <s-vadapalli@ti.com> says: This series adds PCIe endpoint boot support for the TI J784S4 SoC. Series is based on commit f9ffeec4bdc ("board: toradex: Make A53 get RAM size from DT in K3 boards") of the master branch of U-Boot. PCIe Boot Logs (J784S4-EVM running Linux as Root-Complex transfers bootloaders to another J784S4-EVM configured for PCIe Boot): https://gist.github.com/Siddharth-Vadapalli-at-TI/2d157003818441fe79a139d0dec1058a Link: https://lore.kernel.org/r/20260216102858.2745657-1-s-vadapalli@ti.com 
Siddharth Vadapalli <s-vadapalli@ti.com> says:

This series adds PCIe endpoint boot support for the TI J784S4 SoC.
Series is based on commit f9ffeec4bdc ("board: toradex: Make A53 get RAM
size from DT in K3 boards") of the master branch of U-Boot.

PCIe Boot Logs (J784S4-EVM running Linux as Root-Complex transfers
bootloaders to another J784S4-EVM configured for PCIe Boot):
https://gist.github.com/Siddharth-Vadapalli-at-TI/2d157003818441fe79a139d0dec1058a

Link: https://lore.kernel.org/r/20260216102858.2745657-1-s-vadapalli@ti.com
phy: ti: Add config to enable J721E WIZ SERDES wrapper at SPL stage 2026-03-16T14:24:04+00:00 Hrushikesh Salunke h-salunke@ti.com 2026-02-16T10:28:31+00:00 35e1083fb930ba1fa3a3c5cd139bf8285043c191 Add SPL_PHY_J721E_WIZ configuration option to enable the WIZ SERDES wrapper driver in SPL stage. This is required for PCIe boot support where SERDES configuration must be done early in the boot sequence before loading the bootloader image over PCIe. Signed-off-by: Hrushikesh Salunke <h-salunke@ti.com> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> 
Add SPL_PHY_J721E_WIZ configuration option to enable the WIZ SERDES
wrapper driver in SPL stage. This is required for PCIe boot support
where SERDES configuration must be done early in the boot sequence
before loading the bootloader image over PCIe.

Signed-off-by: Hrushikesh Salunke <h-salunke@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
phy: cadence: Add config to enable Cadence Torrent PHY at SPL stage 2026-03-16T14:24:03+00:00 Hrushikesh Salunke h-salunke@ti.com 2026-02-16T10:28:30+00:00 2a21f48771a2f4f0f05d9c76517212ffb94f3c35 Add SPL_PHY_CADENCE_TORRENT configuration option to enable the Cadence Torrent PHY driver in SPL stage. This is required for PCIe boot support where SERDES configuration must be done early in the boot sequence before loading the bootloader image over PCIe. Signed-off-by: Hrushikesh Salunke <h-salunke@ti.com> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> 
Add SPL_PHY_CADENCE_TORRENT configuration option to enable the Cadence
Torrent PHY driver in SPL stage. This is required for PCIe boot support
where SERDES configuration must be done early in the boot sequence
before loading the bootloader image over PCIe.

Signed-off-by: Hrushikesh Salunke <h-salunke@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Merge tag 'u-boot-rockchip-20260309' of https://source.denx.de/u-boot/custodians/u-boot-rockchip into next 2026-03-10T16:07:04+00:00 Tom Rini trini@konsulko.com 2026-03-10T14:17:13+00:00 d93a63acfe701aa07c9223ec454164c88e7eb43d CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/29452 - New SoC support: RK3506, RK3582; - New Board support: RK3528 FriendlyElec NanoPi Zero2; - Other fixes 
CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/29452

- New SoC support: RK3506, RK3582;
- New Board support: RK3528 FriendlyElec NanoPi Zero2;
- Other fixes
phy: rockchip-inno-usb2: Add support for RK3506 2026-03-10T16:07:03+00:00 Jonas Karlman jonas@kwiboo.se 2026-01-31T23:38:21+00:00 7404646f038f7a834fb40f38ce44a45c54471032 Add support for the two USB2.0 PHYs use in the RK3506 SoC. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Tested-by: Aaron Griffith <aargri@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> 
Add support for the two USB2.0 PHYs use in the RK3506 SoC.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Tested-by: Aaron Griffith <aargri@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Merge tag 'v2026.04-rc4' into next 2026-03-09T21:26:34+00:00 Tom Rini trini@konsulko.com 2026-03-09T21:26:34+00:00 1e240f7206fccde4ec73ea432ab8360d321c5fe5 Prepare v2026.04-rc4 
Prepare v2026.04-rc4
phy: rockchip: naneng-combphy: Enable U3 port for USB3OTG on RK3568 2026-03-09T14:48:31+00:00 Jonas Karlman jonas@kwiboo.se 2026-01-06T23:36:43+00:00 fe54fdc6f6ccbdf30b37ef4cc879b74b5e027d6a The USB OTG U3 port may have been disabled early, add support to the COMBPHY driver to re-enable the U3 port. This matches changes made in the Linux commit 7bb14b61b7d0 ("phy: rockchip: naneng-combphy: Enable U3 OTG port for RK3568"). Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Acked-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> 
The USB OTG U3 port may have been disabled early, add support to the
COMBPHY driver to re-enable the U3 port.

This matches changes made in the Linux commit 7bb14b61b7d0 ("phy:
rockchip: naneng-combphy: Enable U3 OTG port for RK3568").

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Acked-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
phy: Add MediaTek UFS PHY Driver 2026-03-02T14:19:17+00:00 Igor Belwon igor.belwon@mentallysanemainliners.org 2025-10-11T19:10:04+00:00 25f142543196e5b5f0f9c916f15671dcd26eb2f7 This UFS M-PHY driver can be used on recent MediaTek SoCs as the primary PHY for the UFS controller. Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org> Link: https://patch.msgid.link/20251011-mtk-ufs-uboot-v1-1-a05f991ee150@mentallysanemainliners.org Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> 
This UFS M-PHY driver can be used on recent MediaTek SoCs as the
primary PHY for the UFS controller.

Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org>
Link: https://patch.msgid.link/20251011-mtk-ufs-uboot-v1-1-a05f991ee150@mentallysanemainliners.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-samsung 2026-02-25T14:49:28+00:00 Tom Rini trini@konsulko.com 2026-02-25T14:49:28+00:00 7995bf8dea2d5b3eb7fcb836636f4773924ec35d - Assorted platform and video driver updates 
- Assorted platform and video driver updates
phy: samsung: add support for exynos7870 USB PHY 2026-02-25T01:46:05+00:00 Kaustabh Chakraborty kauschluss@disroot.org 2026-02-23T14:25:24+00:00 e4001865ff387b928ea3d422d673dcc7389f8665 The USB PHY used by the Exynos7870 SoC has a single USB 2.0 interface. Add its dedicated variant enum, compatible, and init/exit functions. The PHY enable bit of Exynos7870's PHY is different in contrast to that of Exynos850 and most Exynos PHYs. To allow this change, a simple if condition is added in exynos_usbdrd_phy_isol() which changes the bitmask. Since the variant enum is required, the function argument is changed to accept the driver data itself. Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org> Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> 
The USB PHY used by the Exynos7870 SoC has a single USB 2.0 interface.
Add its dedicated variant enum, compatible, and init/exit functions.

The PHY enable bit of Exynos7870's PHY is different in contrast to that
of Exynos850 and most Exynos PHYs. To allow this change, a simple if
condition is added in exynos_usbdrd_phy_isol() which changes the
bitmask. Since the variant enum is required, the function argument is
changed to accept the driver data itself.

Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>