Add a PHY driver for the R-Car Gen2 which allows configuring the mux
connected to the EHCI controllers and USBHS controller.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

The code fails to copy the last PHY phandle argument, so it is
missing from the adjusted phandle args and the consumer cannot
use it to determine what the PHY should do.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>

Only H3 and H5 have 4 PHYS so restrict rst_mask only for them
by checking PHY id as 3 and update the proper bits.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>

usb_clk_cfg is setting CTRL_PHYGATE bit value in probe
which is BIT 0 for sun4i, 6i and 8 for a83t but all
these were handling in phy ops init exit calls.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>

On newer Allwinner SoC, there is a pair of EHCI/OHCI USB hosts
for OTG host mode. USB PHY passby must be configured for its
corresponding PHY. so we can call for PHY#0. on the other hand
in past usb-phy code the same thing can be restricted for
Lower SoC's, other than H3/H5/A64.

Now there is no need to restrict usb passby since the phy driver
is DT enabled, and the respective phy calls will trigger based
DT information initiated by the drivers.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>

In case of phy are provided from a PHY provider nodes as following:

usbphyc: usb-phy@5a006000 {
	compatible = "st,stm32mp1-usbphyc";
	reg = <0x5a006000 0x1000>;
	clocks = <&rcc_clk USBPHY_K>;
	resets = <&rcc_rst USBPHY_R>;
	#address-cells = <1>;
	#size-cells = <0>;

	usbphyc_port0: usb-phy@0 {
		reg = <0>;
		phy-supply = <&vdd_usb>;
		vdda1v1-supply = <&reg11>;
		vdda1v8-supply = <&reg18>
		#phy-cells = <0>;
	};

	usbphyc_port1: usb-phy@1 {
		reg = <1>;
		phy-supply = <&vdd_usb>;
		vdda1v1-supply = <&reg11>;
		vdda1v8-supply = <&reg18>
		#phy-cells = <1>;
	};
};

and PHY are called as following:

usbh_ehci: usbh-ehci@5800d000 {
	compatible = "generic-ehci";
	reg = <0x5800d000 0x1000>;
	clocks = <&rcc_clk USBH>;
	resets = <&rcc_rst USBH_R>;
	interrupts = <GIC_SPI 75 IRQ_TYPE_NONE>;
	companion = <&usbh_ohci>;
	phys = <&usbphyc_port0>;
	phy-names = "usb";
	status = "okay";
};

generic_phy_get_by_index() must be updated to first look for
PHY phandle as previously and in case of error looks for PHY
provider by finding the parent's current node which is the PHY
provider.
args (ofnode_phandle_args struct) must also be updated by inserting
the phy index into the PHY provider as args[0].

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

Also fix bad accents in my name.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

Also fix bad accents in my name.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

Also fix bad accents in my name.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>