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<title>u-boot.git/drivers/phy, branch v2019.07-rc2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>phy: meson: add Amlogic G12A USB2 and USB3+PCIE PHY drivers</title>
<updated>2019-05-09T08:38:32+00:00</updated>
<author>
<name>Neil Armstrong</name>
<email>narmstrong@baylibre.com</email>
</author>
<published>2019-02-19T14:17:29+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=277d9167cb413f6e3a40dc03cfa02a13fe93ec3f'/>
<id>277d9167cb413f6e3a40dc03cfa02a13fe93ec3f</id>
<content type='text'>
This adds support for the USB PHYs found in the Amlogic G12A SoC Family.

The USB2 PHY supports Host and/or Peripheral mode, depending on it's position.
The first PHY is only used as Host, but the second supports Dual modes
defined by the USB Control Glue HW in front of the USB Controllers.

The second driver supports USB3 Host mode or PCIE 2.0 mode, depending on
the layout of the board.
Selection is done by the #phy-cells, making the mode static and exclusive.

Signed-off-by: Neil Armstrong &lt;narmstrong@baylibre.com&gt;
</content>
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<pre>
This adds support for the USB PHYs found in the Amlogic G12A SoC Family.

The USB2 PHY supports Host and/or Peripheral mode, depending on it's position.
The first PHY is only used as Host, but the second supports Dual modes
defined by the USB Control Glue HW in front of the USB Controllers.

The second driver supports USB3 Host mode or PCIE 2.0 mode, depending on
the layout of the board.
Selection is done by the #phy-cells, making the mode static and exclusive.

Signed-off-by: Neil Armstrong &lt;narmstrong@baylibre.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>phy: usbphyc: increase PLL wait timeout</title>
<updated>2019-04-21T08:26:51+00:00</updated>
<author>
<name>Patrick Delaunay</name>
<email>patrick.delaunay@st.com</email>
</author>
<published>2019-03-29T14:42:13+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=901f6950a482d11849b7c748eaef7bda010e91dc'/>
<id>901f6950a482d11849b7c748eaef7bda010e91dc</id>
<content type='text'>
wait 200us to solve USB init issue on device mode
(ums and stm32prog commands)

Signed-off-by: Patrick Delaunay &lt;patrick.delaunay@st.com&gt;
</content>
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<pre>
wait 200us to solve USB init issue on device mode
(ums and stm32prog commands)

Signed-off-by: Patrick Delaunay &lt;patrick.delaunay@st.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>phy: usbphyc: move vdda1v1 and vdda1v8 in phy_init</title>
<updated>2019-04-21T08:26:51+00:00</updated>
<author>
<name>Patrick Delaunay</name>
<email>patrick.delaunay@st.com</email>
</author>
<published>2019-03-29T14:42:12+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e1904abc1bf90e9b382042a45d645d3dd6fbe8b0'/>
<id>e1904abc1bf90e9b382042a45d645d3dd6fbe8b0</id>
<content type='text'>
vdda1v1 and vdda1v8 are used by the PLL.
Both need to be enabled before starting the PLL.

Signed-off-by: Patrick Delaunay &lt;patrick.delaunay@st.com&gt;
</content>
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<pre>
vdda1v1 and vdda1v8 are used by the PLL.
Both need to be enabled before starting the PLL.

Signed-off-by: Patrick Delaunay &lt;patrick.delaunay@st.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>phy: usbphyc: Binding update of vdda supply</title>
<updated>2019-04-21T08:26:51+00:00</updated>
<author>
<name>Patrick Delaunay</name>
<email>patrick.delaunay@st.com</email>
</author>
<published>2019-03-29T14:42:11+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c50151d43f78738d3d9fef4c4f4611e83178dc88'/>
<id>c50151d43f78738d3d9fef4c4f4611e83178dc88</id>
<content type='text'>
Move supply vdda1v1 and vdda1v8 in usbphyc node and
no more in port

Signed-off-by: Patrick Delaunay &lt;patrick.delaunay@st.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Move supply vdda1v1 and vdda1v8 in usbphyc node and
no more in port

Signed-off-by: Patrick Delaunay &lt;patrick.delaunay@st.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>phy: usbphyc: update xlate with DT binding</title>
<updated>2019-04-21T08:26:51+00:00</updated>
<author>
<name>Patrick Delaunay</name>
<email>patrick.delaunay@st.com</email>
</author>
<published>2019-03-29T14:42:10+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1655f2da8449db915fe414e3f88e64ad64f6a77a'/>
<id>1655f2da8449db915fe414e3f88e64ad64f6a77a</id>
<content type='text'>
Parameter added for port 1, for example:

&amp;usbh_ehci {
	phys = &lt;&amp;usbphyc_port0&gt;;
	phy-names = "usb";
	vbus-supply = &lt;&amp;vbus_sw&gt;;
	status = "okay";
};

&amp;usbotg_hs {
	pinctrl-names = "default";
	pinctrl-0 = &lt;&amp;usbotg_hs_pins_a&gt;;
	phys = &lt;&amp;usbphyc_port1 0&gt;;
	phy-names = "usb2-phy";
	status = "okay";
};

Signed-off-by: Patrick Delaunay &lt;patrick.delaunay@st.com&gt;
</content>
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<pre>
Parameter added for port 1, for example:

&amp;usbh_ehci {
	phys = &lt;&amp;usbphyc_port0&gt;;
	phy-names = "usb";
	vbus-supply = &lt;&amp;vbus_sw&gt;;
	status = "okay";
};

&amp;usbotg_hs {
	pinctrl-names = "default";
	pinctrl-0 = &lt;&amp;usbotg_hs_pins_a&gt;;
	phys = &lt;&amp;usbphyc_port1 0&gt;;
	phy-names = "usb2-phy";
	status = "okay";
};

Signed-off-by: Patrick Delaunay &lt;patrick.delaunay@st.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>phy: usbphyc: remove unused variable index</title>
<updated>2019-04-21T08:26:51+00:00</updated>
<author>
<name>Patrick Delaunay</name>
<email>patrick.delaunay@st.com</email>
</author>
<published>2019-03-29T14:42:09+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=6841d83cec269d5b926f3bce5d60f840d03ee507'/>
<id>6841d83cec269d5b926f3bce5d60f840d03ee507</id>
<content type='text'>
Remove unused field index in struct stm32_usbphyc_phy.

Signed-off-by: Patrick Delaunay &lt;patrick.delaunay@st.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Remove unused field index in struct stm32_usbphyc_phy.

Signed-off-by: Patrick Delaunay &lt;patrick.delaunay@st.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>phy: Add USB PHY driver for the MT76x8 (7628/7688) SoC</title>
<updated>2019-04-12T15:32:53+00:00</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2019-04-05T11:44:43+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d7d7606c7e3f78fa201280f5af08ddae238233a1'/>
<id>d7d7606c7e3f78fa201280f5af08ddae238233a1</id>
<content type='text'>
This driver is derived from this Linux driver:
linux/drivers/phy/ralink/phy-ralink-usb.c

The driver sets up power and host mode, but also needs to configure PHY
registers for the MT7628 and MT7688.

I removed the reset controller handling for the USB host and device, as
it does not seem to be necessary right now. The soft reset bits for both
devices are enabled by default and testing has shown (with hackish
reset handling added), that USB related commands work identical with
or without the reset handling.

Please note that the resulting USB support is tested only very minimal.
I was able to detect one of my 3 currently available USB sticks.
Perhaps some further work is needed to fully support the EHCI controller
integrated in the MT76x8 SoC.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Cc: Marek Vasut &lt;marex@denx.de&gt;
Cc: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
</content>
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<pre>
This driver is derived from this Linux driver:
linux/drivers/phy/ralink/phy-ralink-usb.c

The driver sets up power and host mode, but also needs to configure PHY
registers for the MT7628 and MT7688.

I removed the reset controller handling for the USB host and device, as
it does not seem to be necessary right now. The soft reset bits for both
devices are enabled by default and testing has shown (with hackish
reset handling added), that USB related commands work identical with
or without the reset handling.

Please note that the resulting USB support is tested only very minimal.
I was able to detect one of my 3 currently available USB sticks.
Perhaps some further work is needed to fully support the EHCI controller
integrated in the MT76x8 SoC.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Cc: Marek Vasut &lt;marex@denx.de&gt;
Cc: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>phy: Also allow MESON_GXM for MESON_GXL_USB_PHY</title>
<updated>2019-04-03T14:23:38+00:00</updated>
<author>
<name>Neil Armstrong</name>
<email>narmstrong@baylibre.com</email>
</author>
<published>2019-04-03T11:46:36+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=82548aaad57b4060e57dfecc7752253eb3534474'/>
<id>82548aaad57b4060e57dfecc7752253eb3534474</id>
<content type='text'>
The MESON_GXL_USB_PHY is also used on the Amlogic Meson GXM SoCs.

Fixes: 2960e27e38 ("phy: Add Amlogic Meson USB2 &amp; USB3 Generic PHY drivers")
Signed-off-by: Neil Armstrong &lt;narmstrong@baylibre.com&gt;
</content>
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<pre>
The MESON_GXL_USB_PHY is also used on the Amlogic Meson GXM SoCs.

Fixes: 2960e27e38 ("phy: Add Amlogic Meson USB2 &amp; USB3 Generic PHY drivers")
Signed-off-by: Neil Armstrong &lt;narmstrong@baylibre.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>phy: sun4i-usb: Use CLK and RESET support</title>
<updated>2019-01-18T16:49:09+00:00</updated>
<author>
<name>Jagan Teki</name>
<email>jagan@amarulasolutions.com</email>
</author>
<published>2018-08-06T06:46:39+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=089ffd0aedb76f1408c651090b3bbfeb1449d582'/>
<id>089ffd0aedb76f1408c651090b3bbfeb1449d582</id>
<content type='text'>
Now clock and reset drivers are available for respective
SoC's so use clk and reset ops on phy driver.

Signed-off-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
Acked-by: Maxime Ripard &lt;maxime.ripard@bootlin.com&gt;
Reviewed-by: Marek Vasut &lt;marex@denx.de&gt;
</content>
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<pre>
Now clock and reset drivers are available for respective
SoC's so use clk and reset ops on phy driver.

Signed-off-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
Acked-by: Maxime Ripard &lt;maxime.ripard@bootlin.com&gt;
Reviewed-by: Marek Vasut &lt;marex@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>phy: omap_usb2: Add support for am437x</title>
<updated>2018-12-14T16:59:09+00:00</updated>
<author>
<name>Jean-Jacques Hiblot</name>
<email>jjhiblot@ti.com</email>
</author>
<published>2018-12-04T10:30:49+00:00</published>
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<id>512a84c4447707439da48297b2062dcfc8be61a1</id>
<content type='text'>
Signed-off-by: Jean-Jacques Hiblot &lt;jjhiblot@ti.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
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<pre>
Signed-off-by: Jean-Jacques Hiblot &lt;jjhiblot@ti.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</pre>
</div>
</content>
</entry>
</feed>
