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<title>u-boot.git/drivers/phy, branch v2020.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>phy: ti-pipe3: Fix SATA &amp; USB PHY power up sequence</title>
<updated>2019-12-26T14:06:54+00:00</updated>
<author>
<name>Roger Quadros</name>
<email>rogerq@ti.com</email>
</author>
<published>2019-11-06T14:21:18+00:00</published>
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<id>305a5d840eb900af9f8682e5dc57e96c2b457e64</id>
<content type='text'>
As per "Table 26-7. SATA PHY Subsystem Low-Level Programming Sequence"
in TRM [1] we need to turn on SATA_PHY_TX before SATA_PHY_RX.

[1] DRA75x, DRA74x TRM - http://www.ti.com/lit/ug/sprui30f/sprui30f.pdf

Signed-off-by: Roger Quadros &lt;rogerq@ti.com&gt;
</content>
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<pre>
As per "Table 26-7. SATA PHY Subsystem Low-Level Programming Sequence"
in TRM [1] we need to turn on SATA_PHY_TX before SATA_PHY_RX.

[1] DRA75x, DRA74x TRM - http://www.ti.com/lit/ug/sprui30f/sprui30f.pdf

Signed-off-by: Roger Quadros &lt;rogerq@ti.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>phy: ti-pipe3: improve DPLL stability for SATA &amp; USB</title>
<updated>2019-12-26T14:06:54+00:00</updated>
<author>
<name>Roger Quadros</name>
<email>rogerq@ti.com</email>
</author>
<published>2019-11-06T14:21:17+00:00</published>
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<content type='text'>
For increased DPLL stability use the settings recommended in
the TRM [1] for PHY_RX registers for SATA and USB.

For SATA we need to use spread spectrum settings even
though we don't have spread spectrum enabled. The
suggested non-spread spectrum settings don't work.

[1] DRA75x, DRA74x TRM - http://www.ti.com/lit/ug/sprui30f/sprui30f.pdf

Signed-off-by: Roger Quadros &lt;rogerq@ti.com&gt;
</content>
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<pre>
For increased DPLL stability use the settings recommended in
the TRM [1] for PHY_RX registers for SATA and USB.

For SATA we need to use spread spectrum settings even
though we don't have spread spectrum enabled. The
suggested non-spread spectrum settings don't work.

[1] DRA75x, DRA74x TRM - http://www.ti.com/lit/ug/sprui30f/sprui30f.pdf

Signed-off-by: Roger Quadros &lt;rogerq@ti.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>phy: ti-pipe3: Introduce mode property in driver data</title>
<updated>2019-12-26T14:06:54+00:00</updated>
<author>
<name>Roger Quadros</name>
<email>rogerq@ti.com</email>
</author>
<published>2019-11-06T14:21:16+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=53df65a9d2bafcd6ef01f27888fb7be61e7bbd08'/>
<id>53df65a9d2bafcd6ef01f27888fb7be61e7bbd08</id>
<content type='text'>
Introduce a mode property in the driver data so that
we don't have to keep using "of_device_is_compatible()"
throughtout the driver.

No functional change.

Signed-off-by: Roger Quadros &lt;rogerq@ti.com&gt;
</content>
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<pre>
Introduce a mode property in the driver data so that
we don't have to keep using "of_device_is_compatible()"
throughtout the driver.

No functional change.

Signed-off-by: Roger Quadros &lt;rogerq@ti.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>phy: ti-pipe3: Use TRM recommended settings for SATA DPLL</title>
<updated>2019-12-26T14:06:54+00:00</updated>
<author>
<name>Roger Quadros</name>
<email>rogerq@ti.com</email>
</author>
<published>2019-11-06T14:21:15+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b055e67f96d69dc0d273588cafa1cab95d1cabea'/>
<id>b055e67f96d69dc0d273588cafa1cab95d1cabea</id>
<content type='text'>
The AM572x Technical Reference Manual, SPRUHZ6H,
Revised November 2016 [1], shows recommended settings for the
SATA DPLL in Table 26-8. DPLL CLKDCOLDO Recommended Settings.

Use those settings in the driver. The TRM does not show
a value for 20MHz SYS_CLK so we use something close to the
26MHz setting.

[1] - http://www.ti.com/lit/ug/spruhz6h/spruhz6h.pdf

Signed-off-by: Roger Quadros &lt;rogerq@ti.com&gt;
</content>
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<pre>
The AM572x Technical Reference Manual, SPRUHZ6H,
Revised November 2016 [1], shows recommended settings for the
SATA DPLL in Table 26-8. DPLL CLKDCOLDO Recommended Settings.

Use those settings in the driver. The TRM does not show
a value for 20MHz SYS_CLK so we use something close to the
26MHz setting.

[1] - http://www.ti.com/lit/ug/spruhz6h/spruhz6h.pdf

Signed-off-by: Roger Quadros &lt;rogerq@ti.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drivers: phy: Handle gracefully NULL pointers</title>
<updated>2019-10-31T11:22:53+00:00</updated>
<author>
<name>Jean-Jacques Hiblot</name>
<email>jjhiblot@ti.com</email>
</author>
<published>2019-10-01T12:03:26+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=4e1842988364446ba0cf2171d1eebb53c15bc44e'/>
<id>4e1842988364446ba0cf2171d1eebb53c15bc44e</id>
<content type='text'>
For some controllers PHYs can be optional. Handling NULL pointers without
crashing nor failing, makes it easy to handle optional PHYs.

Signed-off-by: Jean-Jacques Hiblot &lt;jjhiblot@ti.com&gt;
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<pre>
For some controllers PHYs can be optional. Handling NULL pointers without
crashing nor failing, makes it easy to handle optional PHYs.

Signed-off-by: Jean-Jacques Hiblot &lt;jjhiblot@ti.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge tag 'mips-pull-2019-10-25' of git://git.denx.de/u-boot-mips</title>
<updated>2019-10-26T00:07:24+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2019-10-26T00:07:24+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ffc379b42c85466e1dd4c8fee8268801f26d2ab8'/>
<id>ffc379b42c85466e1dd4c8fee8268801f26d2ab8</id>
<content type='text'>
- bmips: add BCRM NAND support for BCM6368, BCM6328, BCM6362 and BCM63268 SoCs
- bmips: various small fixes
- mtmips: add new drivers for clock, reset-controller and pinctrl
- mtmips: add support for high speed UART
- mtmips: update/enhance drivers for SPI and ethernet
- mtmips: add support for MMC
</content>
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<pre>
- bmips: add BCRM NAND support for BCM6368, BCM6328, BCM6362 and BCM63268 SoCs
- bmips: various small fixes
- mtmips: add new drivers for clock, reset-controller and pinctrl
- mtmips: add support for high speed UART
- mtmips: update/enhance drivers for SPI and ethernet
- mtmips: add support for MMC
</pre>
</div>
</content>
</entry>
<entry>
<title>phy: mt76x8-usb-phy: add slew rate calibration and remove non-mt7628 part</title>
<updated>2019-10-25T15:20:44+00:00</updated>
<author>
<name>Weijie Gao</name>
<email>weijie.gao@mediatek.com</email>
</author>
<published>2019-09-25T09:45:31+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=4cce51141f2d65e3a76b618159cc96dda099810e'/>
<id>4cce51141f2d65e3a76b618159cc96dda099810e</id>
<content type='text'>
This patch adds slew rate calibration for mt76x8-usb-phy, removes code
which belongs to mt7620, and gets rid of using syscon and regmap by using
clock driver and reset controller.

Signed-off-by: Weijie Gao &lt;weijie.gao@mediatek.com&gt;
</content>
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<pre>
This patch adds slew rate calibration for mt76x8-usb-phy, removes code
which belongs to mt7620, and gets rid of using syscon and regmap by using
clock driver and reset controller.

Signed-off-by: Weijie Gao &lt;weijie.gao@mediatek.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>phy: keystone-usb: handle the transition of the USB power domain</title>
<updated>2019-10-24T09:28:17+00:00</updated>
<author>
<name>Jean-Jacques Hiblot</name>
<email>jjhiblot@ti.com</email>
</author>
<published>2019-09-11T09:33:56+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=2bbc1bbf5d66360d330a0358cf03512e86e49122'/>
<id>2bbc1bbf5d66360d330a0358cf03512e86e49122</id>
<content type='text'>
There is no proper power domain support for the keystone platforms.
However we need to turn off the USB domains before jumping to linux or it
fail to boot (observed with k2e and k2l platforms).
This can be done in the PHY driver as it is dedicated only to the keystone
platforms and matches the required on/off sequence.

Signed-off-by: Jean-Jacques Hiblot &lt;jjhiblot@ti.com&gt;
</content>
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<pre>
There is no proper power domain support for the keystone platforms.
However we need to turn off the USB domains before jumping to linux or it
fail to boot (observed with k2e and k2l platforms).
This can be done in the PHY driver as it is dedicated only to the keystone
platforms and matches the required on/off sequence.

Signed-off-by: Jean-Jacques Hiblot &lt;jjhiblot@ti.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>phy: mediatek: add MediaTek T-PHY support for PCIe</title>
<updated>2019-10-11T14:10:18+00:00</updated>
<author>
<name>Ryder Lee</name>
<email>ryder.lee@mediatek.com</email>
</author>
<published>2019-08-22T10:26:50+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=235bad02e57db3f66473c45677a30886ddd01541'/>
<id>235bad02e57db3f66473c45677a30886ddd01541</id>
<content type='text'>
The driver provides PHY for USB2, USB3.0, PCIe and SATA, and now
we just enable PCIe. As for the other functionalities will be
added gradually in upcoming days.

This is adapted from the Linux version.

Tested-by: Frank Wunderlich &lt;frank-w@public-files.de&gt;
Signed-off-by: Ryder Lee &lt;ryder.lee@mediatek.com&gt;
Signed-off-by: Frank Wunderlich &lt;frank-w@public-files.de&gt;
</content>
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<pre>
The driver provides PHY for USB2, USB3.0, PCIe and SATA, and now
we just enable PCIe. As for the other functionalities will be
added gradually in upcoming days.

This is adapted from the Linux version.

Tested-by: Frank Wunderlich &lt;frank-w@public-files.de&gt;
Signed-off-by: Ryder Lee &lt;ryder.lee@mediatek.com&gt;
Signed-off-by: Frank Wunderlich &lt;frank-w@public-files.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Kconfig: Varios: Fix more SPL, TPL dependencies</title>
<updated>2019-08-26T15:46:29+00:00</updated>
<author>
<name>Adam Ford</name>
<email>aford173@gmail.com</email>
</author>
<published>2019-08-24T18:50:34+00:00</published>
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<id>a074667d52031b1074bc23ca59bf0b73c13ccf7c</id>
<content type='text'>
Several options are presenting themselves on a various boards
where the options are clearly not used.  (ie, SPL/TPL options
when SPL or TPL are not defined)

This patch is not attempting to be a complete list of items, but
more like low hanging fruit.  In some instances, I wasn't sure
of DM was required, so I simply made them SPL or TPL.

This patch attempts to reduce some of the menuconfig noise
by defining dependencies so they don't appear when not used.

Signed-off-by: Adam Ford &lt;aford173@gmail.com&gt;
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<pre>
Several options are presenting themselves on a various boards
where the options are clearly not used.  (ie, SPL/TPL options
when SPL or TPL are not defined)

This patch is not attempting to be a complete list of items, but
more like low hanging fruit.  In some instances, I wasn't sure
of DM was required, so I simply made them SPL or TPL.

This patch attempts to reduce some of the menuconfig noise
by defining dependencies so they don't appear when not used.

Signed-off-by: Adam Ford &lt;aford173@gmail.com&gt;
</pre>
</div>
</content>
</entry>
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