u-boot.git/drivers/phy, branch v2022.04-rc2Unnamed repository; edit this file 'description' to name the repository.http://cgit.235523.xyz/u-boot.git/atom/drivers/phy?h=v2022.04-rc22022-02-11T16:29:23Zphy: nop-phy: Enable reset-gpios support2022-02-11T16:29:23ZAdam Fordaford173@gmail.com2022-01-29T13:27:47Zurn:sha1:3970c82a60857b72afcb676697caf9c979dab946
Some usb-nop-xceiv devices use a gpio take them out
of reset. Add a reset function to put them into that
state. This is similar to how Linux handles the
usb-nop-xceiv driver.
Signed-off-by: Adam Ford <aford173@gmail.com>
phy: cadence: Sierra: Add support for skipping configuration2022-02-08T16:00:04ZAswath Govindrajua-govindraju@ti.com2022-01-28T08:11:50Zurn:sha1:68c6476146339bc0a8724e0f6314a3b71a329598
In some cases, a single SerDes instance can be shared between two different
processors, each using a separate link. In these cases, the SerDes
configuration is done in an earlier boot stage. Therefore, add support to
skip reconfiguring, if it is was already configured beforehand.
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration2022-02-08T16:00:04ZSwapnil Jakhadesjakhade@cadence.com2022-01-28T08:11:49Zurn:sha1:fa294b274ba0005fbee5ddd6da15aee5483073ae
Add register sequences for PCIe + QSGMII PHY multilink configuration.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
phy: cadence: Sierra: Add support for PHY multilink configurations2022-02-08T16:00:03ZSwapnil Jakhadesjakhade@cadence.com2022-01-28T08:11:48Zurn:sha1:168fbf79db2aa2b8f123fc3a060f38789e113aa2
Add support for multilink configuration of Sierra PHY. Currently,
maximum two links are supported.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
phy: cadence: Sierra: Update single link PCIe register configuration2022-02-08T16:00:03ZSwapnil Jakhadesjakhade@cadence.com2022-01-28T08:11:47Zurn:sha1:960efc5edce88dda1350f2ca1f92d3f358762112
Add single link PCIe register configurations for no SSC and internal
SSC. Also, add missing PMA lane registers for external SSC.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operation2022-02-08T16:00:03ZSwapnil Jakhadesjakhade@cadence.com2022-01-28T08:11:46Zurn:sha1:f0cb8096d9226d30b95363244287b4524742144d
PIPE phy status is used to communicate the completion of several PHY
functions. Check if PHY is ready for operation while configured for
PIPE mode during startup.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
phy: cadence: Sierra: Check cmn_ready assertion during PHY power on2022-02-08T16:00:03ZSwapnil Jakhadesjakhade@cadence.com2022-01-28T08:11:45Zurn:sha1:48f29871f09dc059646deafa6e7f3b0cc8c892fc
Check if PMA cmn_ready is set indicating the startup process is complete.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
phy: cadence: Sierra: Add PHY PCS common register configurations2022-02-08T16:00:03ZSwapnil Jakhadesjakhade@cadence.com2022-01-28T08:11:44Zurn:sha1:990ce535ebc3f912769cbc8a651b7eb53545c60d
Add PHY PCS common register configuration sequences for single link.
Update single link PCIe register sequence accordingly.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
phy: cadence: Sierra: Rename some regmap variables to be in sync with Sierra documentation2022-02-08T16:00:03ZSwapnil Jakhadesjakhade@cadence.com2022-01-28T08:11:43Zurn:sha1:445c8cf89b7472a6a78854f87de114bc067c1878
No functional change. Rename some regmap variables as mentioned in Sierra
register description documentation.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
phy: cadence: Sierra: Add support to get SSC type from device tree.2022-02-08T16:00:03ZSwapnil Jakhadesjakhade@cadence.com2022-01-28T08:11:42Zurn:sha1:b6541d496f6aa080aa321d587e2e6e4cdc63d14e
Add support to get SSC type from DT.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>