u-boot.git/drivers/phy, branch v2022.04-rc2 Unnamed repository; edit this file 'description' to name the repository. phy: nop-phy: Enable reset-gpios support 2022-02-11T16:29:23+00:00 Adam Ford aford173@gmail.com 2022-01-29T13:27:47+00:00 3970c82a60857b72afcb676697caf9c979dab946 Some usb-nop-xceiv devices use a gpio take them out of reset. Add a reset function to put them into that state. This is similar to how Linux handles the usb-nop-xceiv driver. Signed-off-by: Adam Ford <aford173@gmail.com> 
Some usb-nop-xceiv devices use a gpio take them out
of reset.  Add a reset function to put them into that
state.  This is similar to how Linux handles the
usb-nop-xceiv driver.

Signed-off-by: Adam Ford <aford173@gmail.com>
phy: cadence: Sierra: Add support for skipping configuration 2022-02-08T16:00:04+00:00 Aswath Govindraju a-govindraju@ti.com 2022-01-28T08:11:50+00:00 68c6476146339bc0a8724e0f6314a3b71a329598 In some cases, a single SerDes instance can be shared between two different processors, each using a separate link. In these cases, the SerDes configuration is done in an earlier boot stage. Therefore, add support to skip reconfiguring, if it is was already configured beforehand. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> 
In some cases, a single SerDes instance can be shared between two different
processors, each using a separate link. In these cases, the SerDes
configuration is done in an earlier boot stage. Therefore, add support to
skip reconfiguring, if it is was already configured beforehand.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration 2022-02-08T16:00:04+00:00 Swapnil Jakhade sjakhade@cadence.com 2022-01-28T08:11:49+00:00 fa294b274ba0005fbee5ddd6da15aee5483073ae Add register sequences for PCIe + QSGMII PHY multilink configuration. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> 
Add register sequences for PCIe + QSGMII PHY multilink configuration.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
phy: cadence: Sierra: Add support for PHY multilink configurations 2022-02-08T16:00:03+00:00 Swapnil Jakhade sjakhade@cadence.com 2022-01-28T08:11:48+00:00 168fbf79db2aa2b8f123fc3a060f38789e113aa2 Add support for multilink configuration of Sierra PHY. Currently, maximum two links are supported. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> 
Add support for multilink configuration of Sierra PHY. Currently,
maximum two links are supported.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
phy: cadence: Sierra: Update single link PCIe register configuration 2022-02-08T16:00:03+00:00 Swapnil Jakhade sjakhade@cadence.com 2022-01-28T08:11:47+00:00 960efc5edce88dda1350f2ca1f92d3f358762112 Add single link PCIe register configurations for no SSC and internal SSC. Also, add missing PMA lane registers for external SSC. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> 
Add single link PCIe register configurations for no SSC and internal
SSC. Also, add missing PMA lane registers for external SSC.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operation 2022-02-08T16:00:03+00:00 Swapnil Jakhade sjakhade@cadence.com 2022-01-28T08:11:46+00:00 f0cb8096d9226d30b95363244287b4524742144d PIPE phy status is used to communicate the completion of several PHY functions. Check if PHY is ready for operation while configured for PIPE mode during startup. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> 
PIPE phy status is used to communicate the completion of several PHY
functions. Check if PHY is ready for operation while configured for
PIPE mode during startup.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
phy: cadence: Sierra: Check cmn_ready assertion during PHY power on 2022-02-08T16:00:03+00:00 Swapnil Jakhade sjakhade@cadence.com 2022-01-28T08:11:45+00:00 48f29871f09dc059646deafa6e7f3b0cc8c892fc Check if PMA cmn_ready is set indicating the startup process is complete. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> 
Check if PMA cmn_ready is set indicating the startup process is complete.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
phy: cadence: Sierra: Add PHY PCS common register configurations 2022-02-08T16:00:03+00:00 Swapnil Jakhade sjakhade@cadence.com 2022-01-28T08:11:44+00:00 990ce535ebc3f912769cbc8a651b7eb53545c60d Add PHY PCS common register configuration sequences for single link. Update single link PCIe register sequence accordingly. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> 
Add PHY PCS common register configuration sequences for single link.
Update single link PCIe register sequence accordingly.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
phy: cadence: Sierra: Rename some regmap variables to be in sync with Sierra documentation 2022-02-08T16:00:03+00:00 Swapnil Jakhade sjakhade@cadence.com 2022-01-28T08:11:43+00:00 445c8cf89b7472a6a78854f87de114bc067c1878 No functional change. Rename some regmap variables as mentioned in Sierra register description documentation. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> 
No functional change. Rename some regmap variables as mentioned in Sierra
register description documentation.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
phy: cadence: Sierra: Add support to get SSC type from device tree. 2022-02-08T16:00:03+00:00 Swapnil Jakhade sjakhade@cadence.com 2022-01-28T08:11:42+00:00 b6541d496f6aa080aa321d587e2e6e4cdc63d14e Add support to get SSC type from DT. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> 
Add support to get SSC type from DT.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>