u-boot.git/drivers/phy, branch v2022.10 Unnamed repository; edit this file 'description' to name the repository. phy: stm32-usbphyc: usbphyc is a clock provider of ck_usbo_48m clock 2022-09-06T11:54:50+00:00 Patrick Delaunay patrick.delaunay@foss.st.com 2022-04-26T12:37:48+00:00 9406f9735c998a179d8ecc886ad7d5287473222f ck_usbo_48m is generated by usbphyc PLL and used by OTG controller for Full-Speed use cases with dedicated Full-Speed transceiver. ck_usbo_48m is available as soon as the PLL is enabled. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> 
ck_usbo_48m is generated by usbphyc PLL and used by OTG controller
for Full-Speed use cases with dedicated Full-Speed transceiver.

ck_usbo_48m is available as soon as the PLL is enabled.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
phy: stm32-usbphyc: add counter of PLL consumer 2022-09-06T11:54:50+00:00 Patrick Delaunay patrick.delaunay@foss.st.com 2022-04-26T12:37:47+00:00 3c2db629581fbde2140a5cc6ec4f5b1f2290bda6 Add the counter of the PLL user n_pll_cons managed by the 2 functions stm32_usbphyc_pll_enable / stm32_usbphyc_pll_disable. This counter allow to remove the function stm32_usbphyc_is_init and it is a preliminary step for ck_usbo_48m introduction. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> 
Add the counter of the PLL user n_pll_cons managed by the 2 functions
stm32_usbphyc_pll_enable / stm32_usbphyc_pll_disable.

This counter allow to remove the function stm32_usbphyc_is_init
and it is a preliminary step for ck_usbo_48m introduction.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
phy: ti: j721e-wiz: use OF data for device specific data 2022-07-25T13:38:47+00:00 Matt Ranostay mranostay@ti.com 2022-07-08T06:41:52+00:00 ea3e163f21b65420f0a8e17af519006e69904b43 Move device specific data into OF data structure so it is easier to maintain and we can get rid of if statements. Based on: https://lore.kernel.org/linux-phy/20220526064121.27625-1-rogerq@kernel.org/T/#u Cc: Roger Quadros <rogerq@kernel.org> Signed-off-by: Matt Ranostay <mranostay@ti.com> 
Move device specific data into OF data structure so it
is easier to maintain and we can get rid of if statements.

Based on: https://lore.kernel.org/linux-phy/20220526064121.27625-1-rogerq@kernel.org/T/#u

Cc: Roger Quadros <rogerq@kernel.org>
Signed-off-by: Matt Ranostay <mranostay@ti.com>
phy: sun4i-usb: Add D1 variant 2022-07-18T22:48:37+00:00 Samuel Holland samuel@sholland.org 2022-07-15T04:09:22+00:00 25ba5be1c2b6324917254f0c22df1ad9d3d3c9e7 D1 has a register layout like A100 and H616, with the moved SIDDQ bit. Unlike H616 it does not have any dependencies between PHY instances. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> 
D1 has a register layout like A100 and H616, with the moved SIDDQ bit.
Unlike H616 it does not have any dependencies between PHY instances.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
phy: sun4i-usb: Rework HCI PHY (aka "pmu_unk1") handling 2022-07-18T22:48:30+00:00 Andre Przywara andre.przywara@arm.com 2022-07-15T04:09:21+00:00 b33ee49ac10ce2e400d171c1018db2359b25fb96 As Icenowy pointed out, newer manuals (starting with H6) actually document the register block at offset 0x800 as "HCI controller and PHY interface", also describe the bits in our "PMU_UNK1" register. Let's put proper names to those "unknown" variables and symbols. While we are at it, generalise the existing code by allowing a bitmap of bits to clear and set, to cover newer SoCs: The A100 and H616 use a different bit for the SIDDQ control. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> 
As Icenowy pointed out, newer manuals (starting with H6) actually
document the register block at offset 0x800 as "HCI controller and PHY
interface", also describe the bits in our "PMU_UNK1" register.
Let's put proper names to those "unknown" variables and symbols.

While we are at it, generalise the existing code by allowing a bitmap
of bits to clear and set, to cover newer SoCs: The A100 and H616 use a
different bit for the SIDDQ control.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
phy: sun4i-usb: Drop use of arch-specific headers 2022-07-18T22:48:19+00:00 Samuel Holland samuel@sholland.org 2022-07-15T04:09:20+00:00 64331352cb75b722df848ff11449737fa78204b3 Since commit 089ffd0aedb7 ("phy: sun4i-usb: Use CLK and RESET support") neither of these headers is used. Dropping them allows the driver to be architecture-independent. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> 
Since commit 089ffd0aedb7 ("phy: sun4i-usb: Use CLK and RESET support")
neither of these headers is used. Dropping them allows the driver to be
architecture-independent.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
sunxi: Move INITIAL_USB_SCAN_DELAY to driver Kconfig 2022-07-18T22:48:09+00:00 Samuel Holland samuel@sholland.org 2022-07-15T04:09:19+00:00 a35628ec33a12032b82cc7be58f8b41c7ab0a4b2 This option is used only by the phy-sun4i-usb driver, which does not inherently depend on the ARM architecture. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> 
This option is used only by the phy-sun4i-usb driver, which does not
inherently depend on the ARM architecture.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
phy: mtk-tphy: add support for MediaTek MT7621 SoC 2022-07-13T21:03:37+00:00 Weijie Gao weijie.gao@mediatek.com 2022-05-20T03:23:01+00:00 be3dc920988df180182f263524d536772cc16986 This patch makes mtk-tphy driver available for MediaTek MT7621 SoC Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> 
This patch makes mtk-tphy driver available for MediaTek MT7621 SoC

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Merge branch 'next' 2022-07-11T18:58:57+00:00 Tom Rini trini@konsulko.com 2022-07-11T14:18:13+00:00 36b661dc919da318c163a45f4a220d2e3d9db608 






phy: nuvoton: add NPCM7xx phy control driver
2022-07-06T18:30:51+00:00

Jim Liu
jim.t90615@gmail.com

2022-06-21T09:03:38+00:00

fdd08f896bcfc513a4cb7799d0094e4fabc73531

add BMC NPCM750 phy control driver

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>





add BMC NPCM750 phy control driver

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>