u-boot.git/drivers/phy, branch v2023.01-rc2 Unnamed repository; edit this file 'description' to name the repository. phy: ti: j721e-wiz: add j784s4-wiz-10g module support 2022-10-18T13:48:22+00:00 Matt Ranostay mranostay@ti.com 2022-10-05T20:51:30+00:00 28ba10074bc9ede42bdc3f717d1c6b1f85a6790d Add support for j784s4-wiz-10g device which has two core reference clocks (e.g core_ref_clk, core_ref1_clk) which requires an additional mux selection option. Signed-off-by: Matt Ranostay <mranostay@ti.com> 
Add support for j784s4-wiz-10g device which has two core reference
clocks (e.g core_ref_clk, core_ref1_clk) which requires an additional
mux selection option.

Signed-off-by: Matt Ranostay <mranostay@ti.com>
phy: Add generic_{setup,shutdown}_phy() helpers 2022-10-10T16:08:18+00:00 Patrice Chotard patrice.chotard@foss.st.com 2022-09-06T06:15:26+00:00 84e561407a5f62a8746dcf8f920e4682690435a0 In drivers usb/host/{ehci,ohci}-generic.c, {ehci,ohci}_setup_phy() and {ehci,ohci}_shutdown_phy() shares 95% of common code. Factorize this code in new generic_{setup,shudown}_phy() functions. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org> 
In drivers usb/host/{ehci,ohci}-generic.c, {ehci,ohci}_setup_phy() and
{ehci,ohci}_shutdown_phy() shares 95% of common code.
Factorize this code in new generic_{setup,shudown}_phy() functions.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Merge branch 'master' into next 2022-09-19T20:07:12+00:00 Tom Rini trini@konsulko.com 2022-09-19T17:19:39+00:00 e9a1ff9724348408144c7f1c5b5cc26130ba46e5 Signed-off-by: Tom Rini <trini@konsulko.com> 
Signed-off-by: Tom Rini <trini@konsulko.com>
phy: stm32-usbphyc: usbphyc is a clock provider of ck_usbo_48m clock 2022-09-06T11:54:50+00:00 Patrick Delaunay patrick.delaunay@foss.st.com 2022-04-26T12:37:48+00:00 9406f9735c998a179d8ecc886ad7d5287473222f ck_usbo_48m is generated by usbphyc PLL and used by OTG controller for Full-Speed use cases with dedicated Full-Speed transceiver. ck_usbo_48m is available as soon as the PLL is enabled. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> 
ck_usbo_48m is generated by usbphyc PLL and used by OTG controller
for Full-Speed use cases with dedicated Full-Speed transceiver.

ck_usbo_48m is available as soon as the PLL is enabled.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
phy: stm32-usbphyc: add counter of PLL consumer 2022-09-06T11:54:50+00:00 Patrick Delaunay patrick.delaunay@foss.st.com 2022-04-26T12:37:47+00:00 3c2db629581fbde2140a5cc6ec4f5b1f2290bda6 Add the counter of the PLL user n_pll_cons managed by the 2 functions stm32_usbphyc_pll_enable / stm32_usbphyc_pll_disable. This counter allow to remove the function stm32_usbphyc_is_init and it is a preliminary step for ck_usbo_48m introduction. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> 
Add the counter of the PLL user n_pll_cons managed by the 2 functions
stm32_usbphyc_pll_enable / stm32_usbphyc_pll_disable.

This counter allow to remove the function stm32_usbphyc_is_init
and it is a preliminary step for ck_usbo_48m introduction.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
phy: Add support for drivers to enable USB on QCS404 SoC 2022-08-26T14:55:45+00:00 Sumit Garg sumit.garg@linaro.org 2022-08-04T14:27:10+00:00 0b746d287c6c467972522da02b836f567e3ed981 QCS404 SoC supports two types of PHY, one supports high speed mode or USB2 PHY and the other supports super speed mode or USB3 PHY. So add corresponding PHY drivers. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> 
QCS404 SoC supports two types of PHY, one supports high speed mode or
USB2 PHY and the other supports super speed mode or USB3 PHY. So add
corresponding PHY drivers.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
phy: Move qcom SoCs specific phy drivers to qcom folder 2022-08-26T14:55:45+00:00 Sumit Garg sumit.garg@linaro.org 2022-08-04T14:27:09+00:00 23ba5f34c8e13e65e8d3749bad610d56fc4814cc Signed-off-by: Sumit Garg <sumit.garg@linaro.org> 
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
phy: ti: j721e-wiz: use OF data for device specific data 2022-07-25T13:38:47+00:00 Matt Ranostay mranostay@ti.com 2022-07-08T06:41:52+00:00 ea3e163f21b65420f0a8e17af519006e69904b43 Move device specific data into OF data structure so it is easier to maintain and we can get rid of if statements. Based on: https://lore.kernel.org/linux-phy/20220526064121.27625-1-rogerq@kernel.org/T/#u Cc: Roger Quadros <rogerq@kernel.org> Signed-off-by: Matt Ranostay <mranostay@ti.com> 
Move device specific data into OF data structure so it
is easier to maintain and we can get rid of if statements.

Based on: https://lore.kernel.org/linux-phy/20220526064121.27625-1-rogerq@kernel.org/T/#u

Cc: Roger Quadros <rogerq@kernel.org>
Signed-off-by: Matt Ranostay <mranostay@ti.com>
phy: sun4i-usb: Add D1 variant 2022-07-18T22:48:37+00:00 Samuel Holland samuel@sholland.org 2022-07-15T04:09:22+00:00 25ba5be1c2b6324917254f0c22df1ad9d3d3c9e7 D1 has a register layout like A100 and H616, with the moved SIDDQ bit. Unlike H616 it does not have any dependencies between PHY instances. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> 
D1 has a register layout like A100 and H616, with the moved SIDDQ bit.
Unlike H616 it does not have any dependencies between PHY instances.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
phy: sun4i-usb: Rework HCI PHY (aka "pmu_unk1") handling 2022-07-18T22:48:30+00:00 Andre Przywara andre.przywara@arm.com 2022-07-15T04:09:21+00:00 b33ee49ac10ce2e400d171c1018db2359b25fb96 As Icenowy pointed out, newer manuals (starting with H6) actually document the register block at offset 0x800 as "HCI controller and PHY interface", also describe the bits in our "PMU_UNK1" register. Let's put proper names to those "unknown" variables and symbols. While we are at it, generalise the existing code by allowing a bitmap of bits to clear and set, to cover newer SoCs: The A100 and H616 use a different bit for the SIDDQ control. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> 
As Icenowy pointed out, newer manuals (starting with H6) actually
document the register block at offset 0x800 as "HCI controller and PHY
interface", also describe the bits in our "PMU_UNK1" register.
Let's put proper names to those "unknown" variables and symbols.

While we are at it, generalise the existing code by allowing a bitmap
of bits to clear and set, to cover newer SoCs: The A100 and H616 use a
different bit for the SIDDQ control.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>