u-boot.git/drivers/phy, branch v2023.04

drivers: phy: add naneng combphy for rk3568

2023-02-28T10:07:27+00:00

RK3568 has three combo phys, and PCIe/USB3/SATA/QSGMII controllers
share one pipe interface for each combo phy, here is the diagram
of the complex connection.

+----------------+
|                |     +------+
| USB3 OTG CTRL0 |---->|      |
|                |     |      |     +------------+
+----------------+     | PIPE |     |            |
                       | MUX  |---->| Combo PHY0 |
+----------------+     |      |     |            |
|                |     |      |     +------------+
|   SATA CTRL0   |---->|      |
|                |     +------+
+----------------+

+----------------+
|                |     +------+
| USB3 HOST CTRL1|---->|      |
|                |     |      |     +------------+
+----------------+     | PIPE |     |            |
                       | MUX  |---->| Combo PHY1 |
+----------------+     |      |     |            |
|                |---->|      |     +------------+
|   SATA CTRL1   |  -->|      |
|                |  |  +------+
+----------------+  |
                    |
+----------------+  |
|                |  |  +------+
|  QSGMII CTRL   |---->|      |
|                |     |      |     +------------+
+----------------+     | PIPE |     |            |
                       | MUX  |---->| Combo PHY2 |
+----------------+     |      |     |            |
|                |---->|      |     +------------+
|   SATA CTRL2   |  -->|      |
|                |  |  +------+
+----------------+  |
                    |
+----------------+  |
|                |  |
|  PCIe2 1-Lane  |---
|                |
+----------------+

Co-developed-by: Manoj Sai 
Signed-off-by: Manoj Sai 
Co-developed-by: Yifeng Zhao 
Signed-off-by: Yifeng Zhao 
Signed-off-by: Jagan Teki 
Reviewed-by: Kever Yang

phy: rockchip-inno-usb2: Add USB2 PHY for rk3568

2023-02-28T10:07:27+00:00

RK3568 has two USB 2.0 PHYs, and each PHY has two ports, the OTG port
of PHY0 support OTG mode with charging detection function, they are
similar to previous Rockchip SoCs.

However, there are three different designs for RK3568 USB 2.0 PHY.
1. RK3568 uses independent USB GRF module for each USB 2.0 PHY.
2. RK3568 accesses the registers of USB 2.0 PHY IP directly by APB.
3. The two ports of USB 2.0 PHY share one interrupt.

This patch only PHY1 with necessary attributes required to function
USBPHY1 on U-Boot.

Co-developed-by: Ren Jianing 
Signed-off-by: Ren Jianing 
Co-developed-by: Jagan Teki 
Signed-off-by: Jagan Teki 
Signed-off-by: Manoj Sai 
Reviewed-by: Kever Yang

phy: rockchip: inno-usb2: Add support #address_cells = 2

2023-02-28T10:07:27+00:00

New Rockchip devices have the usb phy nodes as standalone devices.
These nodes have register nodes with #address_cells = 2, but only
use 32 bit addresses.

Adjust the driver to check if the returned address is "0", and adjust
the index in that case.

Derived and adjusted the similar change from linux-next with below
 commit <9c19c531dc98> ("phy: phy-rockchip-inno-usb2: support
 #address_cells = 2")

Co-developed-by: Manoj Sai 
Signed-off-by: Manoj Sai 
Signed-off-by: Jagan Teki 
Reviewed-by: Kever Yang

Correct SPL uses of USB_MUSB_HOST

2023-02-10T12:41:40+00:00

This converts 2 usages of this option to the non-SPL form, since there is
no SPL_USB_MUSB_HOST defined in Kconfig

Signed-off-by: Simon Glass

global: Finish CONFIG -> CFG migration

2023-01-20T17:27:24+00:00

At this point, the remaining places where we have a symbol that is
defined as CONFIG_... are in fairly odd locations. While as much dead
code has been removed as possible, some of these locations are simply
less obvious at first. In other cases, this code is used, but was
defined in such a way as to have been missed by earlier checks.  Perform
a rename of all such remaining symbols to be CFG_... rather than
CONFIG_...

Signed-off-by: Tom Rini 
Reviewed-by: Simon Glass

phy: rockchip: handle clock without enable function

2022-12-19T02:56:12+00:00

If a clock doesn't supply the enable hook, clk_enable() will return
-ENOSYS.  In this case the clock is always enabled so there is no error
and the phy initialisation should continue.

Signed-off-by: John Keeping 
Reviewed-by: Kever Yang

phy: usbphyc: use regulator_set_enable_if_allowed for disabling vbus supply

2022-12-12T10:25:19+00:00

Use regulator_set_enable_if_allowed() api instead of regulator_set_enable()
while disabling vbus supply. This way the driver doesn't see an error
when it disable an always-on regulator for VBUS.

This patch is needed for STM32MP157C-DK2 board when the regulator
v3v3: buck4 used as the phy vbus supply in kernel device tree
is always on with the next hack for low power use-case:

&usbphyc_port0 {
        ...
	/*
	 * Hack to keep hub active until all connected devices are suspended
	 * otherwise the hub will be powered off as soon as the v3v3 is disabled
	 * and it can disturb connected devices.
	 */
	connector {
		compatible = "usb-a-connector";
		vbus-supply = <&v3v3>;
	};
};

Without this patch and the previous update in DT the command
"usb stop" failed and the next command "usb start" cause a crash.

Signed-off-by: Patrick Delaunay 
Reviewed-by: Patrice Chotard 
Reviewed-by: Marek Vasut

phy: ti: j721e-wiz: add j784s4-wiz-10g module support

2022-10-18T13:48:22+00:00

Add support for j784s4-wiz-10g device which has two core reference
clocks (e.g core_ref_clk, core_ref1_clk) which requires an additional
mux selection option.

Signed-off-by: Matt Ranostay

phy: Add generic_{setup,shutdown}_phy() helpers

2022-10-10T16:08:18+00:00

In drivers usb/host/{ehci,ohci}-generic.c, {ehci,ohci}_setup_phy() and
{ehci,ohci}_shutdown_phy() shares 95% of common code.
Factorize this code in new generic_{setup,shudown}_phy() functions.

Signed-off-by: Patrice Chotard 
Cc: Marek Vasut 
Cc: Simon Glass

Merge branch 'master' into next

2022-09-19T20:07:12+00:00

Signed-off-by: Tom Rini