u-boot.git/drivers/phy, branch v2023.10

phy: phy-imx8mq-usb: clean up clock code

2023-08-25T00:36:19+00:00

use CONFIG_IS_ENABLED for clock enable/disable and change printf's
to dev_err. Additionlly remove the comment that does not make sense.

Signed-off-by: Tim Harvey 
Reviewed-by: Marek Vasut

phy: phy-imx8mq-usb: add vbus regulator support

2023-08-25T00:36:19+00:00

Add support for enabling and disabling vbus-supply regulator found
on several imx8mp boards in the usb3_phy0 and usb3_phy1 nodes.

Signed-off-by: Tim Harvey 
Reviewed-by: Adam Ford 
Reviewed-by: Marek Vasut 
Tested-by: Marcel Ziswiler

phy: rockchip-inno-usb2: Add USB2 PHY for RK3328

2023-07-31T12:33:18+00:00

USB2.0 Host and OTG controllers in RK3328 are using USB2PHY.

Add support for it.

Signed-off-by: Jagan Teki 
Reviewed-by: Xavier Drudis Ferran 
Reviewed-by: Kever Yang

phy: rockchip: add usbdp combo phy driver

2023-07-28T10:45:02+00:00

This adds a new USBDP combo PHY with Samsung IP block driver.
The PHY is a combo between USB 3.0 and DisplayPort alt mode.

Signed-off-by: Frank Wang 
[eugen.hristev@collabora.com: ported to 2023.07, clean-up]
Signed-off-by: Eugen Hristev 
Reviewed-by: Kever Yang

phy: sun4i: Add H616 USB PHY support

2023-07-20T23:28:13+00:00

Now that the Allwinner USB PHY driver supports the H616 quirk, let's
enable support for USB ports on that SoC.

We connect the compatible string to a new struct describing the SoCs USB
PHY properties, and unblock the PHY driver selection in Kconfig.

A later patch will enable USB support in the H616 boards' defconfigs.

Signed-off-by: Andre Przywara 
Reviewed-by: Jernej Skrabec

phy: sun4i-usb: Add H616 USB PHY quirk support

2023-07-20T23:28:13+00:00

The H616 USB PHY is some kind of special snowflake: Only port2 works out
of the box, but all other ports need some help from this port2 to work
correctly: The CLK_BUS_PHY2 and RST_USB_PHY2 clock and reset need to be
enabled, and the SIDDQ bit in the PMU PHY control register needs to be
cleared. For this register to be accessible, CLK_BUS_ECHI2 needs to be
ungated. Don't ask ....

Follow the respective Linux patch (b45c6d80325b) and add a quirk bit,
triggering the special sequence as outlined above, for PHYs other than
PHY2: ungate this one special clock, and clear the SIDDQ bit. We also
pick the clock and reset from PHY2 and enable them as well.

Signed-off-by: Andre Przywara 
Reviewed-by: Jernej Skrabec

phy: sun4i-usb: Replace types with explicit quirk flags

2023-07-20T23:28:13+00:00

So far we were assigning some crude "type" (SoC name, really) to each
Allwinner USB PHY model, then guarding certain quirks based on this.
This does not only look weird, but gets more or more cumbersome to
maintain.

Remove the bogus type names altogether, instead introduce flags for each
quirk, and explicitly check for them.
This improves readability, and simplifies future extensions.

Port of Linux patch 8dd256bae653.

Signed-off-by: Andre Przywara 
Reviewed-by: Jernej Skrabec

sunxi: Kconfig: rework PHY_USB_SUN4I selection

2023-07-20T23:26:36+00:00

At the moment we use "select" in each Allwinner SoC's Kconfig section to
include the USB PHY driver in the build. This means it cannot be disabled
via Kconfig, although USB is not really a strictly required core
functionality, and a particular board might not even include USB ports.

Rework the Kconfig part by removing the "select" lines for each SoC's
section, and instead letting it default to "y" in the PHY driver section
itself. We use "depends on !" to exclude the few SoCs we don't support
(yet). The Allwinner V3s does not enable USB (PHY) support at the moment,
even though it should work: let the PHY default to "n" to keep the
current behaviour.

Also the MUSB USB driver directly calls some functions from the PHY
driver, so let the former depend on the PHY driver.

Signed-off-by: Andre Przywara 
Reviewed-by: Jernej Skrabec 
Tested-by: Sam Edwards

phy: sun4i-usb: add Allwinner F1C100s support

2023-07-20T23:21:42+00:00

The Allwinner F1C100s implements a single USB PHY, connected to its MUSB
OTG controller. The USB PHY is of the simpler, older type (like the A10),
the only real difference is that it's indeed only one PHY.

Add a struct describing those F1C100s USB PHY properties, and connect it
to the new compatible string.

Signed-off-by: Andre Przywara 
Reviewed-by: Jernej Skrabec

phy: sun4i-usb: Fix of_xlate() argument check

2023-07-20T23:21:42+00:00

In its of_xlate() function, the Allwinner USB PHY driver compares the
args_count variable against the number of implemented USB PHYs, although
this is the *number of arguments* to the DT phandle property. Per the DT
binding for this PHY device, this number is always one, so this check
will always fail if the particular SoC implements exactly one USB PHY.
So far this affected only the V3s (which has USB support disabled), but
the F1C100s also sports one PHY only.

Fix that check to compare args_count against exactly 1, and the args[0]
content (requested PHY number) against the number of implemented PHYs.

This fixes USB operation on the Allwinner V3s and allows to enable USB
on the Allwinner F1C100s SoC.

Signed-off-by: Andre Przywara 
Reviewed-by: Jernej Skrabec