u-boot.git/drivers/phy, branch v2025.10-rc2

phy: samsung: Add Exynos USB DRD PHY driver

2025-07-25T01:17:21Z

Add DM driver for Exynos USB PHY controllers. For now it only supports Exynos850 SoC. Only UTMI+ (USB 2.0) PHY interface is implemented, as Exynos850 doesn't support USB 3.0. Only two clocks are used for this controller: - phy: bus clock, used for PHY registers access - ref: PHY reference clock (OSCCLK) Ported from Linux kernel: drivers/phy/samsung/phy-exynos5-usbdrd.c Signed-off-by: Sam Protsenko Reviewed-by: Mattijs Korpershoek Reviewed-by: Minkyu Kang Signed-off-by: Minkyu Kang

phy: cadence: torrent: add support for three or more links using 2 protocols

2025-06-26T19:48:36Z

This is a port of the corresponding commit in the Linux kernel which adds the same support for the Cadence Torrent driver[0]. The commit message below is taken as-is from the Linux kernel commit being ported. The Torrent SERDES can support at most two different protocols (PHY types). This only mandates that the device-tree sub-nodes used to represent the configuration should describe links with at-most two different protocols. The existing implementation however imposes an artificial constraint that allows only two links (device-tree sub-nodes). As long as at-most two protocols are chosen, using more than two links to describe them in an alternating configuration is still a valid configuration of the Torrent SERDES. A 3-Link 2-Protocol configuration of the 4-Lane SERDES can be: Lane 0 => Protocol 1 => Link 1 Lane 1 => Protocol 1 => Link 1 Lane 2 => Protocol 2 => Link 2 Lane 3 => Protocol 1 => Link 3 A 4-Link 2-Protocol configuration of the 4-Lane SERDES can be: Lane 0 => Protocol 1 => Link 1 Lane 1 => Protocol 2 => Link 2 Lane 2 => Protocol 1 => Link 3 Lane 3 => Protocol 2 => Link 4 [0] https://github.com/torvalds/linux/commit/5b7b83a9839be643410c31d56f17c2d430245813 Signed-off-by: Hrushikesh Salunke

phy: qcom: Enable QMP UFS PHY driver for QCS615

2025-06-24T13:54:49Z

Enable QMP phy for QCS615, referenced from Linux. Reviewed-by: Neil Armstrong Signed-off-by: Aswin Murugan Link: https://lore.kernel.org/r/20250521035324.1182833-3-aswin.murugan@oss.qualcomm.com Signed-off-by: Casey Connolly

phy: qcom: Enable QMP UFS PHY driver for QCS8300

2025-06-24T13:54:23Z

Enable QMP phy for QCS8300, referenced from Linux. Reviewed-by: Casey Connolly Reviewed-by: Neil Armstrong Signed-off-by: Balaji Selvanathan Link: https://lore.kernel.org/r/20250529154931.1879976-5-quic_bselvana@quicinc.com Signed-off-by: Casey Connolly

Merge patch series "Hex value prefix case cleanup"

2025-06-14T15:10:48Z

E Shattow says: Make consistent use of lowercase hexadecimal prefix '0x' throughout U-Boot. There are a few remaining uses of uppercase 'X' to denote hexadecimal prefix or placeholder in documentation and error messages. External devicetree-rebasing dts/upstream and the generated code of xilinx/zynq are ignored for the series. Link: https://lore.kernel.org/r/20250606224558.1117422-1-e@freeshell.de

drivers: use lowercase hex prefix style

2025-06-14T15:09:39Z

Use consistent lowercase hex prefix style in drivers/* Does not change hex prefix case in allcaps uppercase style error messages Signed-off-by: E Shattow

phy: stm32-usbphyc: manage properly the clk identifier with CCF

2025-06-11T07:42:55Z

Add private uclass data for "stm32-usbphyc-clk" as it is not done by the driver model. This clk struct is needed by CCF to save the unique id used to identify each clock. Signed-off-by: Patrick Delaunay Signed-off-by: Patrice Chotard Cc: Lukasz Majewski Cc: Sean Anderson Reviewed-by: Patrick Delaunay Reviewed-by: Patrice Chotard

phy: zynqmp: Fix sgmii clk ctrl GTR lane bit shift

2025-06-02T07:13:48Z

The bitshift in GEM_CLK_CTRL register is five bits, not two. There are four bits for each GEM, and one bit reserved in between. This has caused that using more than one GEM is impossible, additionally corrupting the GEM0's configuration, leaving GEM0 unusable as well (ie. if GEM0 and GEM1 are used, GEM1 configuration is going to write to GEM0's registers wrong value, leaving GEM0 unusable) Signed-off-by: Frantisek Bohacek Link: https://lore.kernel.org/r/20250522060703.4863-1-rutherther@ditigal.xyz Signed-off-by: Michal Simek

phy: sun4i-usb: Determine USB OTG detection pin from devicetree

2025-04-28T18:45:44Z

So far Allwinner boards controlled the USB OTG ID detection via the respective GPIO pin specified in Kconfig, as a string. All boards should have the same GPIO already specified in the devicetree, in the usb0_id_det-gpios property. Convert the usage of the Kconfig configured GPIO over to query that information from the devicetree, then use the existing DM GPIO infrastructure to request the GPIO. Only PHY0 supports USB-OTG, so limit the GPIO request to that PHY, to avoid claiming it multiple times. This removes the need to name that GPIO in the defconfig file. Signed-off-by: Andre Przywara Reviewed-by: Jernej Skrabec

phy: sun4i-usb: Determine VBUS detection pin from devicetree

2025-04-28T18:45:44Z

So far Allwinner boards controlled the USB VBUS detection via the respective GPIO pin specified in Kconfig, as a string. All boards should have the same GPIO already specified in the devicetree, in the usb0_vbus_det-gpios property. Convert the usage of the Kconfig configured GPIO over to query that information from the devicetree, then use the existing DM GPIO infrastructure to request the GPIO. Only PHY0 supports USB-OTG, so limit the GPIO request to that PHY, to avoid claiming it multiple times. This removes the need to name that GPIO in the defconfig file. Signed-off-by: Andre Przywara Reviewed-by: Jernej Skrabec