Add support for QCS615 QUSB2 PHY by introducing platform-specific
initialization table and register layout. The implementation reuses
the IPQ6018 register layout and defines QCS615-specific tuning
parameters for proper USB PHY operation.
Taken from Linux commit 8adbf20e0502 ("phy: qcom-qusb2: Add support for QCS615")
Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patch.msgid.link/20260213-talos_usb-v1-3-4c4355d61437@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
This UFS M-PHY driver can be used on recent MediaTek SoCs as the primary PHY for the UFS controller. Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org> Link: https://patch.msgid.link/20251011-mtk-ufs-uboot-v1-1-a05f991ee150@mentallysanemainliners.org Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
- Assorted platform and video driver updates
The USB PHY used by the Exynos7870 SoC has a single USB 2.0 interface. Add its dedicated variant enum, compatible, and init/exit functions. The PHY enable bit of Exynos7870's PHY is different in contrast to that of Exynos850 and most Exynos PHYs. To allow this change, a simple if condition is added in exynos_usbdrd_phy_isol() which changes the bitmask. Since the variant enum is required, the function argument is changed to accept the driver data itself. Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org> Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
The variant enum is used to uniquely identify which SoC the PHY block belongs to. It is initially set in the match table, along with the compatible string, it gets copied to driver data struct during probe. SoC specific functions must only be called if the respective variant enum is set. Add switch-case blocks wherever required. Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org> Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
George McCollister <george.mccollister@konsulko.com> says: This patch series brings over several changes from Linux that are required to get PCIe working on the j722s and also enables PCIe in j722s_evm_a53_defconfig. This allows Linux to be booted from an NVMe drive. The J722S SoC provides pcie0 (using pcie_cdns_ti) thru serdes1 (using phy-cadence-torrent) thru serdes_wiz1 (using phy-j721e-wiz). Changes to the three drivers needed to be ported from Linux to enable the REFCLK output which is used with this SoC. These changes should be tested on other platforms using these drivers by those with the hardware available to make sure no problems were introduced. The PCIe controller in this SoC relies on the code performing the PCI scan not scanning devices which cannot exist. In Linux this is implemented as only_one_child() in probe.c. If this mechanism is not used, PCI config reads for subsequent functions will return information for device 0 resulting in U-Boot detecting 32 devices when only 1 is present. This change should be tested on other platforms with PCI to ensure the same PCI devices are enumerated before and after the patch is applied. I would like to thank Opto 22 for sponsoring the initial development and anyone that is able to contribute to testing of patches. Link: https://lore.kernel.org/r/20260130153856.2049575-1-george.mccollister@konsulko.com
cmn_refclk_<p/m> lines in Torrent SERDES are used for connecting an external reference clock. cmn_refclk_<p/m> can also be configured to output the reference clock. Model this derived reference clock as a "clock" so that platforms like AM642 EVM can enable it. This is used by PCIe to use the same refclk both in local SERDES and remote device. Add support here to drive refclk out. Based on: https://lore.kernel.org/all/20210310120840.16447-7-kishon@ti.com/ Signed-off-by: George McCollister <george.mccollister@konsulko.com> Tested-by: Bryan Brattlof <bb@ti.com>
cmn_refclk_<p/m> lines in Torrent SERDES are used for an connecting external reference clock. cmn_refclk_<p/m> can also be configured to output the reference clock. In order to drive the refclk out from the SERDES (Cadence Torrent), PHY_EN_REFCLK should be set in SERDES_RST of WIZ. Model PHY_EN_REFCLK as a clock, so that platforms like AM642 EVM can enable it. Based on: https://lore.kernel.org/r/20210310120840.16447-6-kishon@ti.com Signed-off-by: George McCollister <george.mccollister@konsulko.com> Tested-by: Bryan Brattlof <bb@ti.com>
AMD/Xilinx/FPGA changes for v2026.04-rc1 v2 microblaze: - Fix spl_boot_list order versal2: - Fix EMMC distro boot setup - Align distro boot variables with memory layout zynqmp-phy: - Sync with Linux kernel driver zynqmp: - Add verify_auth command - DT sync - Add placing variables to FAT/EXT4 - Enable PCIe driver by default pcie - xilinx-nwl: - Fix Link down crash ufs: - Align clock/reset with DT binding # -----BEGIN PGP SIGNATURE----- # # iHUEABYIAB0WIQSXAixArPbWpRanWW+rB/7wTvUR9QUCaW3p3wAKCRCrB/7wTvUR # 9VkwAP4jPRALpM34VpTimNe/iwigIx8hAHxbvkUU0oJ/DW6W8AEAhCSL+ydgreuv # kKCyNiOF1sm8IrOh4TdtMIFn37d4Dwg= # =AkKK # -----END PGP SIGNATURE----- # gpg: Signature made Mon 19 Jan 2026 02:22:55 AM CST # gpg: using EDDSA key 97022C40ACF6D6A516A7596FAB07FEF04EF511F5 # gpg: Can't check signature: No public key
This change is imported from Linux driver and tested with SM6125 SoC. Note, the msm8996_phy_cfg struct is same as sdm660_phy_cfg but qusb2_phy_cfg::se_clk_scheme_default differs only. Signed-off-by: Biswapriyo Nath <nathbappai@gmail.com> Reviewed-by: Casey Connolly <casey.connolly@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Link: https://patch.msgid.link/20251207184919.12202-1-nathbappai@gmail.com Signed-off-by: Casey Connolly <casey.connolly@linaro.org>