u-boot.git/drivers/phy, branch v2026.04-rc1

Merge tag 'xilinx-for-v2026.04-rc1-v2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

2026-01-19T19:08:48Z

AMD/Xilinx/FPGA changes for v2026.04-rc1 v2 microblaze: - Fix spl_boot_list order versal2: - Fix EMMC distro boot setup - Align distro boot variables with memory layout zynqmp-phy: - Sync with Linux kernel driver zynqmp: - Add verify_auth command - DT sync - Add placing variables to FAT/EXT4 - Enable PCIe driver by default pcie - xilinx-nwl: - Fix Link down crash ufs: - Align clock/reset with DT binding # -----BEGIN PGP SIGNATURE----- # # iHUEABYIAB0WIQSXAixArPbWpRanWW+rB/7wTvUR9QUCaW3p3wAKCRCrB/7wTvUR # 9VkwAP4jPRALpM34VpTimNe/iwigIx8hAHxbvkUU0oJ/DW6W8AEAhCSL+ydgreuv # kKCyNiOF1sm8IrOh4TdtMIFn37d4Dwg= # =AkKK # -----END PGP SIGNATURE----- # gpg: Signature made Mon 19 Jan 2026 02:22:55 AM CST # gpg: using EDDSA key 97022C40ACF6D6A516A7596FAB07FEF04EF511F5 # gpg: Can't check signature: No public key

phy: Add MSM8996 support to Qualcomm QUSB2 phy

2026-01-14T15:25:09Z

This change is imported from Linux driver and tested with SM6125 SoC. Note, the msm8996_phy_cfg struct is same as sdm660_phy_cfg but qusb2_phy_cfg::se_clk_scheme_default differs only. Signed-off-by: Biswapriyo Nath Reviewed-by: Casey Connolly Reviewed-by: Sumit Garg Link: https://patch.msgid.link/20251207184919.12202-1-nathbappai@gmail.com Signed-off-by: Casey Connolly

phy: qcom: snps-femto-v2: assert reset in probe

2026-01-14T15:25:09Z

The power on function for the phy only deasserts the reset, so the phy might be in a weird state that we don't clean up properly. Assert the reset in probe() so that when we power on we will have the phy in a clean state. Reviewed-by: Neil Armstrong Link: https://patch.msgid.link/20251114144722.173021-2-casey.connolly@linaro.org Signed-off-by: Casey Connolly

phy: zynqmp: Only wait for PLL lock "primary" instances

2026-01-12T12:01:27Z

For PCIe and DisplayPort, the phy instance represents the controller's logical lane. Wait for the instance 0 phy's PLL to lock as other instances will never lock. We do this in xpsgtr_wait_pll_lock so callers don't have to determine the correct lane themselves. The original comment is wrong about cumulative wait times. Since we are just polling a bit, all subsequent waiters will finish immediately. Signed-off-by: Sean Anderson Link: https://lore.kernel.org/r/20240628205540.3098010-4-sean.anderson@linux.dev Signed-off-by: Vinod Koul [ Linux commit 235d8b663ab9e6cc13f8374abfffa559f50b57b6 ] Link: https://lore.kernel.org/r/20260106215501.727524-5-sean.anderson@linux.dev Signed-off-by: Michal Simek

phy: zynqmp: Store instance instead of type

2026-01-12T12:01:27Z

The phy "type" is just the combination of protocol and instance, and is never used apart from that. Store the instance directly, instead of converting to a type first. No functional change intended. Signed-off-by: Sean Anderson Link: https://lore.kernel.org/r/20240628205540.3098010-3-sean.anderson@linux.dev Signed-off-by: Vinod Koul [ Linux commit 6959d2367bc3503ac4ba3eb4ec6584a43150d6b3 ] Link: https://lore.kernel.org/r/20260106215501.727524-4-sean.anderson@linux.dev Signed-off-by: Michal Simek

phy: zynqmp: Enable reference clock correctly

2026-01-12T12:01:27Z

Lanes can use other lanes' reference clocks, as determined by refclk. Use refclk to determine the clock to enable/disable instead of always using the lane's own reference clock. This ensures the clock selected in xpsgtr_configure_pll is the one enabled. For the other half of the equation, always program REF_CLK_SEL even when we are selecting the lane's own clock. This ensures that Linux's idea of the reference clock matches the hardware. We use the "local" clock mux for this instead of going through the ref clock network. Signed-off-by: Sean Anderson Link: https://lore.kernel.org/r/20240628205540.3098010-2-sean.anderson@linux.dev Signed-off-by: Vinod Koul [ Linux commit 687d6bccb28238fcfa65f7c1badfdfeac498c428 ] Fixes: 1d78d683496 ("phy: zynqmp: Add serdes/psgtr driver") Link: https://lore.kernel.org/r/20260106215501.727524-3-sean.anderson@linux.dev Signed-off-by: Michal Simek

phy: zynqmp: Allow variation in refclk rate

2026-01-12T12:01:27Z

Due to limited available frequency ratios, the reference clock rate may not be exactly the same as the required rate. Allow a small (100 ppm) deviation. Signed-off-by: Sean Anderson Link: https://lore.kernel.org/r/20230711194542.898230-1-sean.anderson@seco.com Signed-off-by: Vinod Koul [ Linux commit 76009ee76e05e30e29aade02e788aebe9ce9ffd2 ] Link: https://lore.kernel.org/r/20260106215501.727524-2-sean.anderson@linux.dev Signed-off-by: Michal Simek

dm: core: Default to using DEVRES outside of xPL

2026-01-09T15:08:14Z

The devm alloc functions that we have may follow the Linux kernel model where allocations are (almost always) automatically free()'d. However, quite often we don't enable, in full U-Boot, the tracking and free()'ing functionality. This in turn leads to memory leaks because the driver author expects that since the functions have the same name as in the Linux Kernel they have the same behavior. In turn we then get functionally correct commits such as commit 00e1fed93c8c ("firmware: ti_sci: Fix memory leaks in devm_ti_sci_get_of_resource") that manually add these calls. Rather than manually tracking allocations and implementing free()s, rework things so that we follow expectations by enabling the DEVRES functionality (outside of xPL phases). This turns DEVRES from a prompted symbol to a symbol that must be select'd, and we now remove our non-managed alloc/free functions from outside of xPL builds. Reviewed-by: Michael Trimarchi Signed-off-by: Tom Rini

phy: renesas: Add Multi-Protocol PHY driver for R-Car X5H

2025-11-06T19:09:58Z

Add PHY driver for Multi-Protocol PHY present on Renesas R-Car X5H R8A78000 SoC. Currently, the PHY driver only supports configuring the MPPHY for ethernet operation. Signed-off-by: Thanh Quan Signed-off-by: Phong Hoang Signed-off-by: Hai Pham #Fix License-Identifier Signed-off-by: Marek Vasut [Marek: Clean up macros, indent, clock and reset handling in probe, rename the driver and add r8a78000- into compatible string, update commit message.]

phy: renesas: Add PCS driver for Renesas R-Car X5H R8A78000

2025-11-06T19:09:58Z

Add support for the Ethernet Physical Coding Sublayer (PCS) controller on R-Car Gen5 SoCs, specifically the Renesas R-Car X5H R8A78000. The controller is based on the SERDES infrastructure used in previous R-Car generations, with updates for Gen5 register layout and features. Because majority of this driver is SoC-specific register programming, the majority of this driver is different enough from R8A779F0 SerDes driver to justify its own driver. Deduplication of the remaining bits of code does not yield any improvement. Signed-off-by: Hai Pham Signed-off-by: Phong Hoang Signed-off-by: Tam Nguyen Signed-off-by: Thanh Quan Signed-off-by: Marek Vasut [Marek: Add missing clk_bulk_disable() in fail path. Drop always-true aneg_on setting. Reduce poll delay from 100s to 100ms. Use bulk reset operations to finalize reset handling.]