u-boot.git/drivers/phy, branch v2026.04-rc2

Merge patch series "arm: k3: j722s: add PCIe support"

2026-02-04T16:40:37+00:00

George McCollister  says:

This patch series brings over several changes from Linux that are required
to get PCIe working on the j722s and also enables PCIe in
j722s_evm_a53_defconfig. This allows Linux to be booted from an NVMe drive.

The J722S SoC provides pcie0 (using pcie_cdns_ti) thru serdes1
(using phy-cadence-torrent) thru serdes_wiz1 (using phy-j721e-wiz). Changes
to the three drivers needed to be ported from Linux to enable the REFCLK
output which is used with this SoC. These changes should be tested on other
platforms using these drivers by those with the hardware available to make
sure no problems were introduced.

The PCIe controller in this SoC relies on the code performing the PCI scan
not scanning devices which cannot exist. In Linux this is implemented as
only_one_child() in probe.c. If this mechanism is not used, PCI config reads
for subsequent functions will return information for device 0 resulting in
U-Boot detecting 32 devices when only 1 is present. This change should be
tested on other platforms with PCI to ensure the same PCI devices are
enumerated before and after the patch is applied.

I would like to thank Opto 22 for sponsoring the initial development and
anyone that is able to contribute to testing of patches.

Link: https://lore.kernel.org/r/20260130153856.2049575-1-george.mccollister@konsulko.com

phy: cadence-torrent: Add support to drive refclk out

2026-02-04T16:40:28+00:00

cmn_refclk_

lines in Torrent SERDES are used for connecting an external reference clock. cmn_refclk_

can also be configured to output the reference clock. Model this derived reference clock as a "clock" so that platforms like AM642 EVM can enable it. This is used by PCIe to use the same refclk both in local SERDES and remote device. Add support here to drive refclk out. Based on: https://lore.kernel.org/all/20210310120840.16447-7-kishon@ti.com/ Signed-off-by: George McCollister Tested-by: Bryan Brattlof

phy: ti: j721e-wiz: Enable reference clock output in cmn_refclk_

2026-02-04T16:40:28+00:00

cmn_refclk_

lines in Torrent SERDES are used for an connecting external reference clock. cmn_refclk_

can also be configured to output the reference clock. In order to drive the refclk out from the SERDES (Cadence Torrent), PHY_EN_REFCLK should be set in SERDES_RST of WIZ. Model PHY_EN_REFCLK as a clock, so that platforms like AM642 EVM can enable it. Based on: https://lore.kernel.org/r/20210310120840.16447-6-kishon@ti.com Signed-off-by: George McCollister Tested-by: Bryan Brattlof

Merge tag 'xilinx-for-v2026.04-rc1-v2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

2026-01-19T19:08:48+00:00

AMD/Xilinx/FPGA changes for v2026.04-rc1 v2

microblaze:
- Fix spl_boot_list order

versal2:
- Fix EMMC distro boot setup
- Align distro boot variables with memory layout

zynqmp-phy:
- Sync with Linux kernel driver

zynqmp:
- Add verify_auth command
- DT sync
- Add placing variables to FAT/EXT4
- Enable PCIe driver by default

pcie - xilinx-nwl:
- Fix Link down crash

ufs:
- Align clock/reset with DT binding

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phy: Add MSM8996 support to Qualcomm QUSB2 phy

2026-01-14T15:25:09+00:00

This change is imported from Linux driver and tested with SM6125 SoC.
Note, the msm8996_phy_cfg struct is same as sdm660_phy_cfg but
qusb2_phy_cfg::se_clk_scheme_default differs only.

Signed-off-by: Biswapriyo Nath 
Reviewed-by: Casey Connolly 
Reviewed-by: Sumit Garg 
Link: https://patch.msgid.link/20251207184919.12202-1-nathbappai@gmail.com
Signed-off-by: Casey Connolly

phy: qcom: snps-femto-v2: assert reset in probe

2026-01-14T15:25:09+00:00

The power on function for the phy only deasserts the reset, so the phy
might be in a weird state that we don't clean up properly.

Assert the reset in probe() so that when we power on we will have the
phy in a clean state.

Reviewed-by: Neil Armstrong 
Link: https://patch.msgid.link/20251114144722.173021-2-casey.connolly@linaro.org
Signed-off-by: Casey Connolly

phy: zynqmp: Only wait for PLL lock "primary" instances

2026-01-12T12:01:27+00:00

For PCIe and DisplayPort, the phy instance represents the controller's
logical lane. Wait for the instance 0 phy's PLL to lock as other
instances will never lock. We do this in xpsgtr_wait_pll_lock so callers
don't have to determine the correct lane themselves.

The original comment is wrong about cumulative wait times. Since we are
just polling a bit, all subsequent waiters will finish immediately.

Signed-off-by: Sean Anderson 
Link: https://lore.kernel.org/r/20240628205540.3098010-4-sean.anderson@linux.dev
Signed-off-by: Vinod Koul 
[ Linux commit 235d8b663ab9e6cc13f8374abfffa559f50b57b6 ]
Link: https://lore.kernel.org/r/20260106215501.727524-5-sean.anderson@linux.dev
Signed-off-by: Michal Simek

phy: zynqmp: Store instance instead of type

2026-01-12T12:01:27+00:00

The phy "type" is just the combination of protocol and instance, and is
never used apart from that. Store the instance directly, instead of
converting to a type first. No functional change intended.

Signed-off-by: Sean Anderson 
Link: https://lore.kernel.org/r/20240628205540.3098010-3-sean.anderson@linux.dev
Signed-off-by: Vinod Koul 
[ Linux commit 6959d2367bc3503ac4ba3eb4ec6584a43150d6b3 ]
Link: https://lore.kernel.org/r/20260106215501.727524-4-sean.anderson@linux.dev
Signed-off-by: Michal Simek

phy: zynqmp: Enable reference clock correctly

2026-01-12T12:01:27+00:00

Lanes can use other lanes' reference clocks, as determined by refclk.
Use refclk to determine the clock to enable/disable instead of always
using the lane's own reference clock. This ensures the clock selected in
xpsgtr_configure_pll is the one enabled.

For the other half of the equation, always program REF_CLK_SEL even when
we are selecting the lane's own clock. This ensures that Linux's idea of
the reference clock matches the hardware. We use the "local" clock mux
for this instead of going through the ref clock network.

Signed-off-by: Sean Anderson 
Link: https://lore.kernel.org/r/20240628205540.3098010-2-sean.anderson@linux.dev
Signed-off-by: Vinod Koul 
[ Linux commit 687d6bccb28238fcfa65f7c1badfdfeac498c428 ]
Fixes: 1d78d683496 ("phy: zynqmp: Add serdes/psgtr driver")
Link: https://lore.kernel.org/r/20260106215501.727524-3-sean.anderson@linux.dev
Signed-off-by: Michal Simek

phy: zynqmp: Allow variation in refclk rate

2026-01-12T12:01:27+00:00

Due to limited available frequency ratios, the reference clock rate may
not be exactly the same as the required rate. Allow a small (100 ppm)
deviation.

Signed-off-by: Sean Anderson 
Link: https://lore.kernel.org/r/20230711194542.898230-1-sean.anderson@seco.com
Signed-off-by: Vinod Koul 
[ Linux commit 76009ee76e05e30e29aade02e788aebe9ce9ffd2 ]
Link: https://lore.kernel.org/r/20260106215501.727524-2-sean.anderson@linux.dev
Signed-off-by: Michal Simek