u-boot.git/drivers/pinctrl/Kconfig, branch main

Merge patch series "pinctrl: aspeed: Add AST2700 pinctrl drivers"

2026-07-14T21:41:13Z

Billy Tsai says: The AST2700 is Aspeed's 7th-generation BMC SoC with a dual-die architecture: SoC0 (CPU die) and SoC1 (I/O die) each have their own SCU with independent multi-function pin controls. Initial AST2700 platform support is already merged in next, including the ast2700.dtsi pinctrl0 and pinctrl1 nodes, but no pinctrl driver backs them yet. This series adds one pinctrl driver per die, each followed by a patch adding its pin configuration support. Both drivers use the generic pinctrl framework and are compatible with the Linux kernel device tree bindings, using the same group and function names as the Linux aspeed,ast2700-soc0/soc1-pinctrl drivers so pin states can be shared between the kernel and U-Boot device trees. Patch 1 adds the SoC0 driver, which models each (function, group) pair as a flat register mask/value table covering eMMC, VB, VGA DDC, JTAG master port select, PCIe RC PERST and USB2/USB3 port routing. Patch 2 adds SoC0 pin configuration support: every GPIO18A/GPIO18B ball has its own IO control register providing a 3 mA to 41 mA drive strength selector and bias control. Patch 3 adds the SoC1 driver, porting the per-pin 4-bit multi-function selector scheme (220 pins, 238 groups, 217 functions) together with the virtual pins for PCIe RC2 PERST, the USB2 port C/D mode and SGMII controls. Patch 4 adds SoC1 pin configuration support: a per-pin bias enable bit and sparse 2-bit drive strength fields (4 mA to 16 mA in 4 mA steps) mirroring the Linux driver layout. The bias-disable, bias-pull-down, bias-pull-up and drive-strength properties can be applied per pin or per group. Both drivers implement gpio_request_enable so the GPIO driver can reclaim pins through the gpio-ranges already present in ast2700.dtsi, and provide get_pin_muxing so "pinmux status" reports the active signal of every pin. Link: https://lore.kernel.org/r/20260702-pinctrl-v1-0-4d2bd89fc213@aspeedtech.com

pinctrl: aspeed: Add AST2700 SoC1 pinconf support

2026-07-14T21:40:20Z

The SoC1 SCU provides a bias enable bit per pin in the registers at 0x480 (setting the bit disables the bias; the pull direction is fixed in silicon) and 2-bit drive strength fields at 0x4C0 selecting 4 mA to 16 mA in 4 mA steps. The pin-to-field mapping of the drive strength registers is sparse and non-linear, so it is kept in a lookup table mirroring the Linux driver; pins without an entry reject drive-strength with -ENOTSUPP. Support the bias-disable, bias-pull-down, bias-pull-up and drive-strength properties per pin and per group, and select PINCONF so the generic pinctrl framework parses them. Signed-off-by: Billy Tsai

pinctrl: aspeed: Add AST2700 SoC1 pinctrl driver

2026-07-14T21:40:20Z

Add the pinctrl driver for the AST2700 SoC1 (I/O) die. Unlike previous Aspeed generations, the SoC1 SCU assigns every pin a 4-bit multi-function selector field in a contiguous register range starting at SCU 0x400, eight pins per register. Only bits [2:0] of each field select the function; bit 3 is reserved read-only and must not be written. The driver therefore keeps per-pin group tables and per-function mux values, mirroring the Linux aspeed,ast2700-soc1-pinctrl driver, and shares the same device tree bindings: 220 pins, 238 groups and 217 functions with identical names, so pin states written for the Linux driver work unmodified. A few controls live outside the pin-indexed range and are handled as virtual pins: PCIERC2_PERST (SCU 0x908), the USB2 port C/D mode fields (SCU 0x3B0) and SGMII0 (SCU 0x47C). The gpio_request_enable hook restores a pin to GPIO by writing mux value 0, except for the ADC-capable balls W17..AB19 where function 1 selects GPIO and 0 selects the ADC input. Signed-off-by: Billy Tsai

pinctrl: aspeed: Add AST2700 SoC0 pinconf support

2026-07-14T21:40:20Z

Each GPIO18A/GPIO18B ball has its own IO control register starting at SCU 0x480, providing a 4-bit drive strength selector (3 mA to 41 mA in hardware-defined steps), a bias enable bit and a pull direction bit. Extend the group table with the pin members of the ball-backed groups so bias-disable, bias-pull-down, bias-pull-up and drive-strength properties can be applied per group as well as per pin. The routing groups (USB, JTAG, PCIe RC) have no package balls and reject pin configuration with -ENOTSUPP. Select PINCONF so the generic pinctrl framework parses the pin configuration properties. Signed-off-by: Billy Tsai

pinctrl: aspeed: Add AST2700 SoC0 pinctrl driver

2026-07-14T21:40:20Z

The AST2700 is a dual-die BMC SoC: SoC0 (CPU die) and SoC1 (I/O die) each have their own SCU with independent multi-function pin controls. Add the pinctrl driver for the SoC0 die. The driver uses the generic pinctrl framework and is compatible with the Linux kernel device tree bindings, i.e. pin states are described with the same "function" and "groups" properties and the same names as the Linux aspeed,ast2700-soc0-pinctrl driver. Unlike the older AST2500/AST2600 SCUs where each signal is enabled by independent bits, the SoC0 mux selections mix single-bit enables (eMMC, VGA DDC, VB strap), multi-bit selector fields (JTAG master port select, USB2/USB3 port routing) and reset-control bits (PCIe RC PERST). Model each (function, group) pair as one register mask/value write so all of them fit a single flat table. The gpio_request_enable hook releases the GPIO18A/GPIO18B pins to GPIO mode by clearing every signal enable bit that claims the pin, matching the Linux driver behaviour. Signed-off-by: Billy Tsai

pinctrl: airoha: add shared pinctrl code

2026-07-08T19:29:18Z

This patch introduce shared Airoha pinctrl code. Also it sorts contents of pinctrl makefile. Signed-off-by: Mikhail Kshevetskiy Reviewed-by: David Lechner

pinctrl: Correct dependencies for PINCTRL_TH1520

2026-03-30T21:02:27Z

As exposed by "make randconfig", we have an issue with the dependencies for PINCTRL_TH1520. It really needs to depend on PINCTRL_GENERIC rather than select it, and PINCTRL_GENERIC in turn already depends on PINCTRL_FULL. Signed-off-by: Tom Rini

scmi: pinctrl: add pinctrl driver for SCMI

2026-03-23T02:58:20Z

This driver adds the base support of pinctrl over SCMI. The driver does two main things. First, it allows you to configure the initial pin states. Secondly, it's used a base to build a GPIO driver on top of it. To configure the states then add a pinmux config to the scmi_pinctrl section: scmi_pinctrl: protocol@19 { reg = <0x19>; pinmux1: pinmux_test { pinmux = <0 1 0xFFFFFFFF 18 1 0 2 0xFFFFFFFF 18 1 0 3 0xFFFFFFFF 18 1>; function = "f_gpio1"; groups = "grp_1", "grp_3"; }; }; Under linux the pinctrl subsystem will parse the function and group properties and use that to handle muxing. However, under u-boot the pin muxing is done using the "pinmux" property, which feeds raw SCMI pinctrl PINCTRL_SETTINGS_CONFIGURE commands to the server. The numbers are: selector, identifier, function_id, config_type, and config_value. In the example above, it sets pins 1, 2, and 3 to 1. The linux-kernel ignores this pinmux property. Signed-off-by: Dan Carpenter Reviewed-by: Peng Fan Signed-off-by: Peng Fan

pinctrl: zynqmp: Add SPL support

2026-02-13T07:16:25Z

Although the pinctrl pm requests are implemented in the PMU firmware, PM_QUERY_DATA is actually implemented in ATF. In SPL (or when running in EL3), ATF is not yet running, so we need to implement this API ourselves. Do the bare minimum, allowing SPL to enumerate functions, but don't bother with groups. Groups take up a lot of space, and can be emulated with pins. For example, a node like display-port { mux { groups = "dpaux0_1"; function = "dpaux0"; }; }; can be replaced by display-port { mux { pins = "MIO34", "MIO35", "MIO36", "MIO37"; function = "dpaux0"; }; }; While this isn't backwards-compatible with existing devicetrees, it's more than enough for SPL where we may only need to mux one or two pins. Add SPL_PINCTRL_ZYNQMP to ensure there's no SPL size growth when pinctrl is enabled in U-Boot but isn't necessary for SPL. The only config this would affect is Kria, but SPL_PINCTRL_GENERIC is disabled so SPL_PINCTRL_ZYNQMP is not selected. Signed-off-by: Sean Anderson Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/20260129184011.3932790-1-sean.anderson@linux.dev

dm: core: Default to using DEVRES outside of xPL

2026-01-09T15:08:14Z

The devm alloc functions that we have may follow the Linux kernel model where allocations are (almost always) automatically free()'d. However, quite often we don't enable, in full U-Boot, the tracking and free()'ing functionality. This in turn leads to memory leaks because the driver author expects that since the functions have the same name as in the Linux Kernel they have the same behavior. In turn we then get functionally correct commits such as commit 00e1fed93c8c ("firmware: ti_sci: Fix memory leaks in devm_ti_sci_get_of_resource") that manually add these calls. Rather than manually tracking allocations and implementing free()s, rework things so that we follow expectations by enabling the DEVRES functionality (outside of xPL phases). This turns DEVRES from a prompted symbol to a symbol that must be select'd, and we now remove our non-managed alloc/free functions from outside of xPL builds. Reviewed-by: Michael Trimarchi Signed-off-by: Tom Rini