<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/drivers/pinctrl/Kconfig, branch v2019.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/pinctrl/Kconfig?h=v2019.01</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/pinctrl/Kconfig?h=v2019.01'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2019-01-02T21:39:12Z</updated>
<entry>
<title>rockchip: rk3399: Add Kconfig option for full pinctrl driver</title>
<updated>2019-01-02T21:39:12Z</updated>
<author>
<name>Christoph Muellner</name>
<email>christoph.muellner@theobroma-systems.com</email>
</author>
<published>2019-01-02T14:09:20Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=8188c83cfa2919a2a8e1d4d1d0daebdad6a1bc99'/>
<id>urn:sha1:8188c83cfa2919a2a8e1d4d1d0daebdad6a1bc99</id>
<content type='text'>
This patch adds a Kconfig option to enable the full pinctrl driver
for the RK3399. This flag needs to be enabed in order to get the
features of the full pinctrl driver compiled in (i.e. a .set_state()
callback).

Signed-off-by: Christoph Muellner &lt;christoph.muellner@theobroma-systems.com&gt;
Reviewed-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
</content>
</entry>
<entry>
<title>pinctrl: mscc: Add gpio and pinctrl driver for MSCC MIPS SoCs (VcoreIII based)</title>
<updated>2018-12-19T14:23:01Z</updated>
<author>
<name>Gregory CLEMENT</name>
<email>gregory.clement@bootlin.com</email>
</author>
<published>2018-12-08T08:59:01Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=53bdae241888de3d23a51735e9610389921b80ae'/>
<id>urn:sha1:53bdae241888de3d23a51735e9610389921b80ae</id>
<content type='text'>
This driver supports the pin and gpio controller found in the Ocelot and
Luton SoCs.

The driver was inspired from the pinctrl driver in Linux, but was
simplified and was modified to allow supporting an other SoCs (Luton).

For Ocelot and Luton the controller is the same, only the pins to program
differ.

Signed-off-by: Gregory CLEMENT &lt;gregory.clement@bootlin.com&gt;
Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
[changed to only descend into mscc/ dependent on CONFIG_PINCTRL_MSCC]
Signed-off-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
</content>
</entry>
<entry>
<title>pinctrl: MediaTek: add pinctrl driver for MT7629 SoC</title>
<updated>2018-11-29T04:04:52Z</updated>
<author>
<name>Ryder Lee</name>
<email>ryder.lee@mediatek.com</email>
</author>
<published>2018-11-15T02:07:58Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=01aa9d1d546f9939261fc262f86698ba2fad0bf8'/>
<id>urn:sha1:01aa9d1d546f9939261fc262f86698ba2fad0bf8</id>
<content type='text'>
This patch adds pinctrl support for MT7629 SoC. The IO core found on
the SoC has the registers for pinctrl, pinconf and gpio mixed up in
the same register range.  Hence the driver also implements the gpio
functionality through UCLASS_GPIO.

This also creates a common file as there might be other chips that use
the same binding and driver, then being a little more abstract could
help in the long run.

Signed-off-by: Ryder Lee &lt;ryder.lee@mediatek.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: Kconfig: Fix typo</title>
<updated>2018-03-05T15:06:05Z</updated>
<author>
<name>Marek Behún</name>
<email>marek.behun@nic.cz</email>
</author>
<published>2018-03-02T08:56:00Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=de2069c761b0e9334b4e68e02f63bf08d8ea1e45'/>
<id>urn:sha1:de2069c761b0e9334b4e68e02f63bf08d8ea1e45</id>
<content type='text'>
Signed-off-by: Marek Behun &lt;marek.behun@nic.cz&gt;
</content>
</entry>
<entry>
<title>bcm283x: Add pinctrl driver</title>
<updated>2018-01-28T17:27:32Z</updated>
<author>
<name>Alexander Graf</name>
<email>agraf@suse.de</email>
</author>
<published>2018-01-23T17:05:21Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=caf2233b281c03e3e359061a3dfa537d8a25c273'/>
<id>urn:sha1:caf2233b281c03e3e359061a3dfa537d8a25c273</id>
<content type='text'>
The bcm283x family of SoCs have a GPIO controller that also acts as
pinctrl controller.

This patch introduces a new pinctrl driver that can actually properly mux
devices into their device tree defined pin states and is now the primary
owner of the gpio device. The previous GPIO driver gets moved into a
subdevice of the pinctrl driver, bound to the same OF node.

That way whenever a device asks for pinctrl support, it gets it
automatically from the pinctrl driver and GPIO support is still available
in the normal command line phase.

Signed-off-by: Alexander Graf &lt;agraf@suse.de&gt;
</content>
</entry>
<entry>
<title>rockchip: rk3128: add pinctrl driver</title>
<updated>2017-11-30T21:55:26Z</updated>
<author>
<name>Kever Yang</name>
<email>kever.yang@rock-chips.com</email>
</author>
<published>2017-11-28T08:04:18Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e129c480e496c2a5e816c7f7e0b27afb3ed037d1'/>
<id>urn:sha1:e129c480e496c2a5e816c7f7e0b27afb3ed037d1</id>
<content type='text'>
Add rk3128 pinctrl driver and grf/iomux structure definition.

Signed-off-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
Acked-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Reviewed-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
</content>
</entry>
<entry>
<title>pinctrl: rmobile: Add Renesas RCar pincontrol driver</title>
<updated>2017-09-27T21:54:06Z</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut@gmail.com</email>
</author>
<published>2017-09-15T19:13:55Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=910df4d07e370dc0dabafaaf85417508cccf43f3'/>
<id>urn:sha1:910df4d07e370dc0dabafaaf85417508cccf43f3</id>
<content type='text'>
Add PFC pincontrol driver for the Renesas RCar Gen3 R8A7795 and R8A7796
SoCs. This driver uses the PFC pin tables from Linux, thus letting us
share the occassional fixes to those tables. This driver also has a DT
support, so the pinmux is configured from DT instead of the ad-hoc setup
in board file.

This driver is meant to replace the pinmux part of SH_GPIO_PFC driver.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
Cc: Nobuhiro Iwamatsu &lt;iwamatsu@nigauri.org&gt;
Signed-off-by: Nobuhiro Iwamatsu &lt;iwamatsu@nigauri.org&gt;
</content>
</entry>
<entry>
<title>dm: Kconfig: fix typo in help for SPL_PINCTRL</title>
<updated>2017-07-31T15:22:53Z</updated>
<author>
<name>Philipp Tomsich</name>
<email>philipp.tomsich@theobroma-systems.com</email>
</author>
<published>2017-07-26T10:27:42Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0fa0abecfc1051b624aff3008a728abe41127b67'/>
<id>urn:sha1:0fa0abecfc1051b624aff3008a728abe41127b67</id>
<content type='text'>
Changes 'controlloers' to 'controllers' in the help-text for
SPL_PINCTRL.

Signed-off-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
</content>
</entry>
<entry>
<title>rockchip: rk322x: add pinctrl driver</title>
<updated>2017-07-11T10:13:46Z</updated>
<author>
<name>Kever Yang</name>
<email>kever.yang@rock-chips.com</email>
</author>
<published>2017-06-23T09:17:50Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5cc9d31a79fecfaacfdbc9c566b6df35765100f8'/>
<id>urn:sha1:5cc9d31a79fecfaacfdbc9c566b6df35765100f8</id>
<content type='text'>
Add init pinctrl driver support for:
- i2c;
- spi;
- uart;
- pwm;
- emmc/sdmmc;

Signed-off-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
Reviewed-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
</content>
</entry>
<entry>
<title>stm32: stm32f7: add spl build support</title>
<updated>2017-06-09T15:23:55Z</updated>
<author>
<name>Vikas Manocha</name>
<email>vikas.manocha@st.com</email>
</author>
<published>2017-05-28T19:55:10Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b97476965bf292c13074e01de4bd39253de0ef66'/>
<id>urn:sha1:b97476965bf292c13074e01de4bd39253de0ef66</id>
<content type='text'>
This commit supports booting from stm32 internal nor flash. spl U-Boot
initializes the sdram memory, copies next image (e.g. standard U-Boot)
to sdram &amp; then jumps to entry point.

Here are the flash memory addresses for U-Boot-spl &amp; standard U-Boot:
	- spl U-Boot		: 0x0800_0000
	- standard U-Boot	: 0x0800_8000

To compile u-boot without spl: Remove SUPPORT_SPL configuration
(arch/arm/mach-stm32/Kconfig)

Signed-off-by: Vikas Manocha &lt;vikas.manocha@st.com&gt;
[trini: Rework Kconfig logic a bit]
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
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