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<title>u-boot.git/drivers/pinctrl/Makefile, branch v2017.05</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>pinctrl: Kconfig: sort pinctrl config options to prevent future clutter</title>
<updated>2017-04-27T20:49:04+00:00</updated>
<author>
<name>Philipp Tomsich</name>
<email>philipp.tomsich@theobroma-systems.com</email>
</author>
<published>2017-04-19T14:46:37+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=51c7f34809dab20e16316a5c4556fbb88c6905a8'/>
<id>51c7f34809dab20e16316a5c4556fbb88c6905a8</id>
<content type='text'>
This originally started out as
     "pinctrl: Kconfig: reorder to keep Rockchip options together"
and tried to keep the Rockchip-related config options together.

However, we now rewrite all chip-specific driver selections to start
with CONFIG_PINCTRL_ (with the inadvertent changes to related
Makefiles) and sort those alphabetically. And as this already means
touching most of the file, we also reformat the help text to not exceed
80 characters (but make full use of those 80 characters).

Signed-off-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
This originally started out as
     "pinctrl: Kconfig: reorder to keep Rockchip options together"
and tried to keep the Rockchip-related config options together.

However, we now rewrite all chip-specific driver selections to start
with CONFIG_PINCTRL_ (with the inadvertent changes to related
Makefiles) and sort those alphabetically. And as this already means
touching most of the file, we also reformat the help text to not exceed
80 characters (but make full use of those 80 characters).

Signed-off-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pinctrl: at91: add pinctrl driver</title>
<updated>2017-04-13T20:44:50+00:00</updated>
<author>
<name>Wenyou Yang</name>
<email>wenyou.yang@atmel.com</email>
</author>
<published>2017-03-23T04:44:37+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=9319a756fffb0aae21adcd7caf8674411a22c165'/>
<id>9319a756fffb0aae21adcd7caf8674411a22c165</id>
<content type='text'>
AT91 PIO controller is a combined gpio-controller, pin-mux and
pin-config module. The peripheral's pins are assigned through
per-pin based muxing logic.

Each SoC will have to describe the its limitation and pin
configuration via device tree. This will allow to do not need
to touch the C code when adding new SoC if the IP version is
supported.

Signed-off-by: Wenyou Yang &lt;wenyou.yang@atmel.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
AT91 PIO controller is a combined gpio-controller, pin-mux and
pin-config module. The peripheral's pins are assigned through
per-pin based muxing logic.

Each SoC will have to describe the its limitation and pin
configuration via device tree. This will allow to do not need
to touch the C code when adding new SoC if the IP version is
supported.

Signed-off-by: Wenyou Yang &lt;wenyou.yang@atmel.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Add single register pin controller driver</title>
<updated>2017-03-26T19:23:42+00:00</updated>
<author>
<name>Felix Brack</name>
<email>fb@ltec.ch</email>
</author>
<published>2017-03-22T10:26:44+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=44d5c371a63e56eb53866b645e75396fa1d95510'/>
<id>44d5c371a63e56eb53866b645e75396fa1d95510</id>
<content type='text'>
This patch adds a pin controller driver supporting devices
using a single configuration register per pin.
Signed-off-by: Felix Brack &lt;fb@ltec.ch&gt;
</content>
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<pre>
This patch adds a pin controller driver supporting devices
using a single configuration register per pin.
Signed-off-by: Felix Brack &lt;fb@ltec.ch&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>PINCTRL: stm32f7: add pin control driver</title>
<updated>2017-03-17T18:15:14+00:00</updated>
<author>
<name>Vikas Manocha</name>
<email>vikas.manocha@st.com</email>
</author>
<published>2017-02-12T18:25:49+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=94d53084120bd977249e78ae4738cc28e62d276d'/>
<id>94d53084120bd977249e78ae4738cc28e62d276d</id>
<content type='text'>
This driver uses the same pin control binding as that of linux, binding
document of this patch is copied from linux. One addition done is for
GPIO input and output mode configuration which was missing.

Signed-off-by: Vikas Manocha &lt;vikas.manocha@st.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
This driver uses the same pin control binding as that of linux, binding
document of this patch is copied from linux. One addition done is for
GPIO input and output mode configuration which was missing.

Signed-off-by: Vikas Manocha &lt;vikas.manocha@st.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>STiH410: Add STi pinctrl driver</title>
<updated>2017-03-15T00:40:20+00:00</updated>
<author>
<name>Patrice Chotard</name>
<email>patrice.chotard@st.com</email>
</author>
<published>2017-02-21T12:37:10+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0c56310252b6fc3c942ec569fefc0dfbc1c38a74'/>
<id>0c56310252b6fc3c942ec569fefc0dfbc1c38a74</id>
<content type='text'>
Add STMicroelectronics STiH410 pinctrl driver

Signed-off-by: Patrice Chotard &lt;patrice.chotard@st.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add STMicroelectronics STiH410 pinctrl driver

Signed-off-by: Patrice Chotard &lt;patrice.chotard@st.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm64: mvebu: pinctrl: Add pin control driver for A8K family</title>
<updated>2016-12-12T08:04:52+00:00</updated>
<author>
<name>Konstantin Porotchkin</name>
<email>kostap@marvell.com</email>
</author>
<published>2016-12-08T10:22:29+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=656e6cc86b96be88f99f6f3ef1df3ef3122a8766'/>
<id>656e6cc86b96be88f99f6f3ef1df3ef3122a8766</id>
<content type='text'>
Add a DM port of Marvell pin control driver.
The A8K SoC family contains several silicone dies interconnected
in a single package. Every die is normally equipped with its own
pin controller unit.
There are 2 pin controllers in A70x0 SoC and 3 in A80x0 SoC.

Signed-off-by: Konstantin Porotchkin &lt;kostap@marvell.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Cc: Simon Glass &lt;sjg@chromium.org&gt;
Cc: Stefan Roese &lt;sr@denx.de&gt;
Cc: Nadav Haklai &lt;nadavh@marvell.com&gt;
Cc: Neta Zur Hershkovits &lt;neta@marvell.com&gt;
Cc: Omri Itach &lt;omrii@marvell.com&gt;
Cc: Igal Liberman &lt;igall@marvell.com&gt;
Cc: Haim Boot &lt;hayim@marvell.com&gt;
Cc: Hanna Hawa &lt;hannah@marvell.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
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<pre>
Add a DM port of Marvell pin control driver.
The A8K SoC family contains several silicone dies interconnected
in a single package. Every die is normally equipped with its own
pin controller unit.
There are 2 pin controllers in A70x0 SoC and 3 in A80x0 SoC.

Signed-off-by: Konstantin Porotchkin &lt;kostap@marvell.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Cc: Simon Glass &lt;sjg@chromium.org&gt;
Cc: Stefan Roese &lt;sr@denx.de&gt;
Cc: Nadav Haklai &lt;nadavh@marvell.com&gt;
Cc: Neta Zur Hershkovits &lt;neta@marvell.com&gt;
Cc: Omri Itach &lt;omrii@marvell.com&gt;
Cc: Igal Liberman &lt;igall@marvell.com&gt;
Cc: Haim Boot &lt;hayim@marvell.com&gt;
Cc: Hanna Hawa &lt;hannah@marvell.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pinctrl: add driver for meson-gxbb pin controller</title>
<updated>2016-09-06T17:18:19+00:00</updated>
<author>
<name>Beniamino Galvani</name>
<email>b.galvani@gmail.com</email>
</author>
<published>2016-08-16T09:49:49+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=677b53580d5d86ca65737497829d581544ae71bf'/>
<id>677b53580d5d86ca65737497829d581544ae71bf</id>
<content type='text'>
Add a pin controller driver for Meson GXBB adapted from Linux kernel.

Signed-off-by: Beniamino Galvani &lt;b.galvani@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add a pin controller driver for Meson GXBB adapted from Linux kernel.

Signed-off-by: Beniamino Galvani &lt;b.galvani@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pinctrl: at91-pio4: Add pinctrl driver</title>
<updated>2016-08-15T20:58:03+00:00</updated>
<author>
<name>Wenyou Yang</name>
<email>wenyou.yang@atmel.com</email>
</author>
<published>2016-07-20T09:16:27+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ac72e174f95ebce2e4a4e2165828223427b2a5f3'/>
<id>ac72e174f95ebce2e4a4e2165828223427b2a5f3</id>
<content type='text'>
AT91 PIO4 controller is a combined gpio-controller, pin-mux and
pin-config module. The peripheral's pins are assigned through
per-pin based muxing logic.

The pin configuration is performed on specific registers which
are shared along with the gpio controller. So regard the pinctrl
device as a child of atmel_pio4 device.

Signed-off-by: Wenyou Yang &lt;wenyou.yang@atmel.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Andreas Bießmann &lt;andreas@biessmann.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
AT91 PIO4 controller is a combined gpio-controller, pin-mux and
pin-config module. The peripheral's pins are assigned through
per-pin based muxing logic.

The pin configuration is performed on specific registers which
are shared along with the gpio controller. So regard the pinctrl
device as a child of atmel_pio4 device.

Signed-off-by: Wenyou Yang &lt;wenyou.yang@atmel.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Andreas Bießmann &lt;andreas@biessmann.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pinctrl: Add pinctrl driver support for Exynos7420 SoC</title>
<updated>2016-05-25T01:00:18+00:00</updated>
<author>
<name>Thomas Abraham</name>
<email>thomas.ab@samsung.com</email>
</author>
<published>2016-04-23T16:48:08+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=16ca80adc551808b6be1d43f30997f8b4fdfbd39'/>
<id>16ca80adc551808b6be1d43f30997f8b4fdfbd39</id>
<content type='text'>
Add pinctrl driver support for Samsung's Exynos7420 SoC. The changes
have been split into Exynos7420 specific and common Exynos specific
portions so that this implementation is reusable on other Exynos
SoCs as well.

The Exynos pinctrl driver supports only device tree based pin
configuration. The bindings used are similar to the ones used in the
linux kernel.

Cc: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Cc: Simon Glass &lt;sjg@chromium.org&gt;
Cc: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
Signed-off-by: Thomas Abraham &lt;thomas.ab@samsung.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Acked-by: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
Signed-off-by: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add pinctrl driver support for Samsung's Exynos7420 SoC. The changes
have been split into Exynos7420 specific and common Exynos specific
portions so that this implementation is reusable on other Exynos
SoCs as well.

The Exynos pinctrl driver supports only device tree based pin
configuration. The bindings used are similar to the ones used in the
linux kernel.

Cc: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Cc: Simon Glass &lt;sjg@chromium.org&gt;
Cc: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
Signed-off-by: Thomas Abraham &lt;thomas.ab@samsung.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Acked-by: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
Signed-off-by: Minkyu Kang &lt;mk7.kang@samsung.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drivers: pinctrl: Add simple pinctrl driver for Qualcomm/Atheros ar933x.</title>
<updated>2016-05-20T23:25:50+00:00</updated>
<author>
<name>Wills Wang</name>
<email>wills.wang@live.com</email>
</author>
<published>2016-03-16T08:59:55+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a79d0643f4cac19711cb8d1c2088fc907d47500f'/>
<id>a79d0643f4cac19711cb8d1c2088fc907d47500f</id>
<content type='text'>
This is a simple pinctrl driver, it just support uart and spi pin-mux now.

Signed-off-by: Wills Wang &lt;wills.wang@live.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
[fixed typo in commit subject line]
Signed-off-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This is a simple pinctrl driver, it just support uart and spi pin-mux now.

Signed-off-by: Wills Wang &lt;wills.wang@live.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
[fixed typo in commit subject line]
Signed-off-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
</pre>
</div>
</content>
</entry>
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