u-boot.git/drivers/pinctrl/Makefile, branch v2017.05-rc1

Add single register pin controller driver

2017-03-26T19:23:42Z

This patch adds a pin controller driver supporting devices using a single configuration register per pin. Signed-off-by: Felix Brack

PINCTRL: stm32f7: add pin control driver

2017-03-17T18:15:14Z

This driver uses the same pin control binding as that of linux, binding document of this patch is copied from linux. One addition done is for GPIO input and output mode configuration which was missing. Signed-off-by: Vikas Manocha Reviewed-by: Simon Glass

STiH410: Add STi pinctrl driver

2017-03-15T00:40:20Z

Add STMicroelectronics STiH410 pinctrl driver Signed-off-by: Patrice Chotard Reviewed-by: Tom Rini Reviewed-by: Simon Glass

arm64: mvebu: pinctrl: Add pin control driver for A8K family

2016-12-12T08:04:52Z

Add a DM port of Marvell pin control driver. The A8K SoC family contains several silicone dies interconnected in a single package. Every die is normally equipped with its own pin controller unit. There are 2 pin controllers in A70x0 SoC and 3 in A80x0 SoC. Signed-off-by: Konstantin Porotchkin Reviewed-by: Simon Glass Cc: Simon Glass Cc: Stefan Roese Cc: Nadav Haklai Cc: Neta Zur Hershkovits Cc: Omri Itach Cc: Igal Liberman Cc: Haim Boot Cc: Hanna Hawa Signed-off-by: Stefan Roese

pinctrl: add driver for meson-gxbb pin controller

2016-09-06T17:18:19Z

Add a pin controller driver for Meson GXBB adapted from Linux kernel. Signed-off-by: Beniamino Galvani Reviewed-by: Simon Glass

pinctrl: at91-pio4: Add pinctrl driver

2016-08-15T20:58:03Z

AT91 PIO4 controller is a combined gpio-controller, pin-mux and pin-config module. The peripheral's pins are assigned through per-pin based muxing logic. The pin configuration is performed on specific registers which are shared along with the gpio controller. So regard the pinctrl device as a child of atmel_pio4 device. Signed-off-by: Wenyou Yang Reviewed-by: Simon Glass Reviewed-by: Andreas Bießmann

pinctrl: Add pinctrl driver support for Exynos7420 SoC

2016-05-25T01:00:18Z

Add pinctrl driver support for Samsung's Exynos7420 SoC. The changes have been split into Exynos7420 specific and common Exynos specific portions so that this implementation is reusable on other Exynos SoCs as well. The Exynos pinctrl driver supports only device tree based pin configuration. The bindings used are similar to the ones used in the linux kernel. Cc: Masahiro Yamada Cc: Simon Glass Cc: Minkyu Kang Signed-off-by: Thomas Abraham Reviewed-by: Simon Glass Acked-by: Minkyu Kang Signed-off-by: Minkyu Kang

drivers: pinctrl: Add simple pinctrl driver for Qualcomm/Atheros ar933x.

2016-05-20T23:25:50Z

This is a simple pinctrl driver, it just support uart and spi pin-mux now. Signed-off-by: Wills Wang Reviewed-by: Simon Glass [fixed typo in commit subject line] Signed-off-by: Daniel Schwierzeck

pinctrl: uniphier: guard uniphier directory with CONFIG_PINCTRL_UNIPHIER

2016-03-08T16:11:04Z

CONFIG_PINCTRL_UNIPHIER is more suitable than CONFIG_ARCH_UNIPHIER to guard the drivers/pinctrl/uniphier directory. The current CONFIG_PINCTRL_UNIPHIER_CORE is a bit long, so rename it into CONFIG_PINCTRL_UNIPHIER. Signed-off-by: Masahiro Yamada

pinctrl: imx: Introduce pinctrl driver for i.MX6

2016-02-21T10:23:48Z

Introduce pinctrl for i.MX6 1. pinctrl-imx.c is for common usage. It's used by i.MX6/7. 2. Add PINCTRL_IMX PINCTRL_IMX6 Kconfig entry. 3. To the pinctrl_ops implementation, only set_state is implemented. To i.MX6/7, the pinctrl dts entry is as following: &iomuxc { pinctrl-names = "default"; pinctrl_csi1: csi1grp { fsl,pins = < MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 >; }; [.....] }; there is no property named function or groups. So pinctrl_generic_set_state can not be used here. 5. This driver is a simple implementation for i.mx iomux controller, only parse the fsl,pins property and write value to registers. 6. With DEBUG enabled, we can see log when "i2c bus 0": " set_state_simple op missing imx_pinctrl_set_state: i2c1grp mux_reg 0x14c, conf_reg 0x3bc, input_reg 0x5d8, mux_mode 0x0, input_val 0x1, config_val 0x4000007f write mux: offset 0x14c val 0x10 select_input: offset 0x5d8 val 0x1 write config: offset 0x3bc val 0x7f mux_reg 0x148, conf_reg 0x3b8, input_reg 0x5d4, mux_mode 0x0, input_val 0x1, config_val 0x4000007f write mux: offset 0x148 val 0x10 select_input: offset 0x5d4 val 0x1 write config: offset 0x3b8 val 0x7f " this means imx6 pinctrl driver works as expected. Signed-off-by: Peng Fan Reviewed-by: Simon Glass