<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/drivers/pinctrl/Makefile, branch v2018.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>pinctrl: rmobile: Add Renesas RCar pincontrol driver</title>
<updated>2017-09-27T21:54:06+00:00</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut@gmail.com</email>
</author>
<published>2017-09-15T19:13:55+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=910df4d07e370dc0dabafaaf85417508cccf43f3'/>
<id>910df4d07e370dc0dabafaaf85417508cccf43f3</id>
<content type='text'>
Add PFC pincontrol driver for the Renesas RCar Gen3 R8A7795 and R8A7796
SoCs. This driver uses the PFC pin tables from Linux, thus letting us
share the occassional fixes to those tables. This driver also has a DT
support, so the pinmux is configured from DT instead of the ad-hoc setup
in board file.

This driver is meant to replace the pinmux part of SH_GPIO_PFC driver.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
Cc: Nobuhiro Iwamatsu &lt;iwamatsu@nigauri.org&gt;
Signed-off-by: Nobuhiro Iwamatsu &lt;iwamatsu@nigauri.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add PFC pincontrol driver for the Renesas RCar Gen3 R8A7795 and R8A7796
SoCs. This driver uses the PFC pin tables from Linux, thus letting us
share the occassional fixes to those tables. This driver also has a DT
support, so the pinmux is configured from DT instead of the ad-hoc setup
in board file.

This driver is meant to replace the pinmux part of SH_GPIO_PFC driver.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
Cc: Nobuhiro Iwamatsu &lt;iwamatsu@nigauri.org&gt;
Signed-off-by: Nobuhiro Iwamatsu &lt;iwamatsu@nigauri.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pinctrl: mvebu: Enable support for the Armada 37xx pinctrl driver</title>
<updated>2017-05-31T05:33:50+00:00</updated>
<author>
<name>Stefan Roese</name>
<email>sr@denx.de</email>
</author>
<published>2017-05-09T11:35:44+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=8dd082a7e65adf342ee24a0d76791759410907ab'/>
<id>8dd082a7e65adf342ee24a0d76791759410907ab</id>
<content type='text'>
To enable support for the Armada 37xx pinctrl driver, we need to
change the Kconfig symbol for the Armada 7k/8k pinctrl driver and its
dependencies to distinguish between both platforms and drivers.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Cc: Konstantin Porotchkin &lt;kostap@marvell.com&gt;
Cc: Nadav Haklai &lt;nadavh@marvell.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
To enable support for the Armada 37xx pinctrl driver, we need to
change the Kconfig symbol for the Armada 7k/8k pinctrl driver and its
dependencies to distinguish between both platforms and drivers.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Cc: Konstantin Porotchkin &lt;kostap@marvell.com&gt;
Cc: Nadav Haklai &lt;nadavh@marvell.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>aspeed: AST2500 Pinctrl Driver</title>
<updated>2017-05-08T15:57:33+00:00</updated>
<author>
<name>maxims@google.com</name>
<email>maxims@google.com</email>
</author>
<published>2017-04-17T19:00:27+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=4f0e44e46615e3c827dcd1ec59677be1058d394c'/>
<id>4f0e44e46615e3c827dcd1ec59677be1058d394c</id>
<content type='text'>
This driver uses Generic Pinctrl framework and is compatible with
the Linux driver for ast2500: it uses the same device tree
configuration.

Not all pins are supported by the driver at the moment, so it actually
compatible with ast2400. In general, however, there are differences that
in the future would be easier to maintain separately.

Signed-off-by: Maxim Sloyko &lt;maxims@google.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This driver uses Generic Pinctrl framework and is compatible with
the Linux driver for ast2500: it uses the same device tree
configuration.

Not all pins are supported by the driver at the moment, so it actually
compatible with ast2400. In general, however, there are differences that
in the future would be easier to maintain separately.

Signed-off-by: Maxim Sloyko &lt;maxims@google.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pinctrl: Kconfig: sort pinctrl config options to prevent future clutter</title>
<updated>2017-04-27T20:49:04+00:00</updated>
<author>
<name>Philipp Tomsich</name>
<email>philipp.tomsich@theobroma-systems.com</email>
</author>
<published>2017-04-19T14:46:37+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=51c7f34809dab20e16316a5c4556fbb88c6905a8'/>
<id>51c7f34809dab20e16316a5c4556fbb88c6905a8</id>
<content type='text'>
This originally started out as
     "pinctrl: Kconfig: reorder to keep Rockchip options together"
and tried to keep the Rockchip-related config options together.

However, we now rewrite all chip-specific driver selections to start
with CONFIG_PINCTRL_ (with the inadvertent changes to related
Makefiles) and sort those alphabetically. And as this already means
touching most of the file, we also reformat the help text to not exceed
80 characters (but make full use of those 80 characters).

Signed-off-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This originally started out as
     "pinctrl: Kconfig: reorder to keep Rockchip options together"
and tried to keep the Rockchip-related config options together.

However, we now rewrite all chip-specific driver selections to start
with CONFIG_PINCTRL_ (with the inadvertent changes to related
Makefiles) and sort those alphabetically. And as this already means
touching most of the file, we also reformat the help text to not exceed
80 characters (but make full use of those 80 characters).

Signed-off-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pinctrl: at91: add pinctrl driver</title>
<updated>2017-04-13T20:44:50+00:00</updated>
<author>
<name>Wenyou Yang</name>
<email>wenyou.yang@atmel.com</email>
</author>
<published>2017-03-23T04:44:37+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=9319a756fffb0aae21adcd7caf8674411a22c165'/>
<id>9319a756fffb0aae21adcd7caf8674411a22c165</id>
<content type='text'>
AT91 PIO controller is a combined gpio-controller, pin-mux and
pin-config module. The peripheral's pins are assigned through
per-pin based muxing logic.

Each SoC will have to describe the its limitation and pin
configuration via device tree. This will allow to do not need
to touch the C code when adding new SoC if the IP version is
supported.

Signed-off-by: Wenyou Yang &lt;wenyou.yang@atmel.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
AT91 PIO controller is a combined gpio-controller, pin-mux and
pin-config module. The peripheral's pins are assigned through
per-pin based muxing logic.

Each SoC will have to describe the its limitation and pin
configuration via device tree. This will allow to do not need
to touch the C code when adding new SoC if the IP version is
supported.

Signed-off-by: Wenyou Yang &lt;wenyou.yang@atmel.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Add single register pin controller driver</title>
<updated>2017-03-26T19:23:42+00:00</updated>
<author>
<name>Felix Brack</name>
<email>fb@ltec.ch</email>
</author>
<published>2017-03-22T10:26:44+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=44d5c371a63e56eb53866b645e75396fa1d95510'/>
<id>44d5c371a63e56eb53866b645e75396fa1d95510</id>
<content type='text'>
This patch adds a pin controller driver supporting devices
using a single configuration register per pin.
Signed-off-by: Felix Brack &lt;fb@ltec.ch&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This patch adds a pin controller driver supporting devices
using a single configuration register per pin.
Signed-off-by: Felix Brack &lt;fb@ltec.ch&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>PINCTRL: stm32f7: add pin control driver</title>
<updated>2017-03-17T18:15:14+00:00</updated>
<author>
<name>Vikas Manocha</name>
<email>vikas.manocha@st.com</email>
</author>
<published>2017-02-12T18:25:49+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=94d53084120bd977249e78ae4738cc28e62d276d'/>
<id>94d53084120bd977249e78ae4738cc28e62d276d</id>
<content type='text'>
This driver uses the same pin control binding as that of linux, binding
document of this patch is copied from linux. One addition done is for
GPIO input and output mode configuration which was missing.

Signed-off-by: Vikas Manocha &lt;vikas.manocha@st.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This driver uses the same pin control binding as that of linux, binding
document of this patch is copied from linux. One addition done is for
GPIO input and output mode configuration which was missing.

Signed-off-by: Vikas Manocha &lt;vikas.manocha@st.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>STiH410: Add STi pinctrl driver</title>
<updated>2017-03-15T00:40:20+00:00</updated>
<author>
<name>Patrice Chotard</name>
<email>patrice.chotard@st.com</email>
</author>
<published>2017-02-21T12:37:10+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0c56310252b6fc3c942ec569fefc0dfbc1c38a74'/>
<id>0c56310252b6fc3c942ec569fefc0dfbc1c38a74</id>
<content type='text'>
Add STMicroelectronics STiH410 pinctrl driver

Signed-off-by: Patrice Chotard &lt;patrice.chotard@st.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add STMicroelectronics STiH410 pinctrl driver

Signed-off-by: Patrice Chotard &lt;patrice.chotard@st.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm64: mvebu: pinctrl: Add pin control driver for A8K family</title>
<updated>2016-12-12T08:04:52+00:00</updated>
<author>
<name>Konstantin Porotchkin</name>
<email>kostap@marvell.com</email>
</author>
<published>2016-12-08T10:22:29+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=656e6cc86b96be88f99f6f3ef1df3ef3122a8766'/>
<id>656e6cc86b96be88f99f6f3ef1df3ef3122a8766</id>
<content type='text'>
Add a DM port of Marvell pin control driver.
The A8K SoC family contains several silicone dies interconnected
in a single package. Every die is normally equipped with its own
pin controller unit.
There are 2 pin controllers in A70x0 SoC and 3 in A80x0 SoC.

Signed-off-by: Konstantin Porotchkin &lt;kostap@marvell.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Cc: Simon Glass &lt;sjg@chromium.org&gt;
Cc: Stefan Roese &lt;sr@denx.de&gt;
Cc: Nadav Haklai &lt;nadavh@marvell.com&gt;
Cc: Neta Zur Hershkovits &lt;neta@marvell.com&gt;
Cc: Omri Itach &lt;omrii@marvell.com&gt;
Cc: Igal Liberman &lt;igall@marvell.com&gt;
Cc: Haim Boot &lt;hayim@marvell.com&gt;
Cc: Hanna Hawa &lt;hannah@marvell.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add a DM port of Marvell pin control driver.
The A8K SoC family contains several silicone dies interconnected
in a single package. Every die is normally equipped with its own
pin controller unit.
There are 2 pin controllers in A70x0 SoC and 3 in A80x0 SoC.

Signed-off-by: Konstantin Porotchkin &lt;kostap@marvell.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Cc: Simon Glass &lt;sjg@chromium.org&gt;
Cc: Stefan Roese &lt;sr@denx.de&gt;
Cc: Nadav Haklai &lt;nadavh@marvell.com&gt;
Cc: Neta Zur Hershkovits &lt;neta@marvell.com&gt;
Cc: Omri Itach &lt;omrii@marvell.com&gt;
Cc: Igal Liberman &lt;igall@marvell.com&gt;
Cc: Haim Boot &lt;hayim@marvell.com&gt;
Cc: Hanna Hawa &lt;hannah@marvell.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pinctrl: add driver for meson-gxbb pin controller</title>
<updated>2016-09-06T17:18:19+00:00</updated>
<author>
<name>Beniamino Galvani</name>
<email>b.galvani@gmail.com</email>
</author>
<published>2016-08-16T09:49:49+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=677b53580d5d86ca65737497829d581544ae71bf'/>
<id>677b53580d5d86ca65737497829d581544ae71bf</id>
<content type='text'>
Add a pin controller driver for Meson GXBB adapted from Linux kernel.

Signed-off-by: Beniamino Galvani &lt;b.galvani@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add a pin controller driver for Meson GXBB adapted from Linux kernel.

Signed-off-by: Beniamino Galvani &lt;b.galvani@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
</feed>
