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<title>u-boot.git/drivers/pinctrl/Makefile, branch v2023.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/pinctrl/Makefile?h=v2023.07</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/pinctrl/Makefile?h=v2023.07'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2023-05-13T02:01:30Z</updated>
<entry>
<title>pinctrl: renesas: add R906G032 driver</title>
<updated>2023-05-13T02:01:30Z</updated>
<author>
<name>Ralph Siemsen</name>
<email>ralph.siemsen@linaro.org</email>
</author>
<published>2023-05-13T01:36:52Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e4aea57fa773ada9443176e2e39af0b4e1750c65'/>
<id>urn:sha1:e4aea57fa773ada9443176e2e39af0b4e1750c65</id>
<content type='text'>
Pinctrl/pinconf driver for Renesas RZ/N1 (R906G032) SoC.

This is quite rudimentary right now, and only supports applying a
default pin configuration as specified by the device tree.

Signed-off-by: Ralph Siemsen &lt;ralph.siemsen@linaro.org&gt;
Reviewed-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: starfive: Add StarFive JH7110 driver</title>
<updated>2023-04-20T08:08:44Z</updated>
<author>
<name>Kuan Lim Lee</name>
<email>kuanlim.lee@linux.starfivetech.com</email>
</author>
<published>2023-03-29T03:42:15Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=732f01aabf53ae97aff9acb92a43c6b3838e6c92'/>
<id>urn:sha1:732f01aabf53ae97aff9acb92a43c6b3838e6c92</id>
<content type='text'>
Add pinctrl driver for StarFive JH7110 SoC.

Signed-off-by: Kuan Lim Lee &lt;kuanlim.lee@linux.starfivetech.com&gt;
Signed-off-by: Emil Renner Berthing &lt;kernel@esmil.dk&gt;
Signed-off-by: Jianlong Huang &lt;jianlong.huang@starfivetech.com&gt;
Signed-off-by: Yanhong Wang &lt;yanhong.wang@starfivetech.com&gt;
Tested-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
</content>
</entry>
<entry>
<title>pinctrl: nuvoton: Add NPCM7xx pinctrl driver</title>
<updated>2022-06-10T17:37:32Z</updated>
<author>
<name>Jim Liu</name>
<email>jim.t90615@gmail.com</email>
</author>
<published>2022-05-17T08:30:32Z</published>
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<id>urn:sha1:f49d616bea2f529b36e2d7fc892c9745eea3bce0</id>
<content type='text'>
Add Nuvoton BMC NPCM750 Pinmux and Pinconf support.

Signed-off-by: Jim Liu &lt;JJLIU0@nuvoton.com&gt;
</content>
</entry>
<entry>
<title>Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi</title>
<updated>2022-04-05T12:33:32Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2022-04-05T12:33:32Z</published>
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<id>urn:sha1:4de720e98d552dfda9278516bf788c4a73b3e56f</id>
<content type='text'>
A big part is the DM pinctrl driver, which allows us to get rid of quite
some custom pinmux code and make the whole port much more robust. Many
thanks to Samuel for that nice contribution! There are some more or less
cosmetic warnings about missing clocks right now, I will send the trivial
fixes for that later.
Another big chunk is the mkimage upgrade, which adds RISC-V and TOC0
(secure images) support. Both features are unused at the moment, but I
have an always-secure board that will use that once the DT lands in the
kernel.
On top of those big things we have some smaller fixes, improving the
I2C DM support, fixing some H6/H616 early clock setup and improving the
eMMC boot partition support.

The gitlab CI completed successfully, including the build test for all
161 sunxi boards. I also boot tested on a A64, A20, H3, H6, and F1C100
board. USB, SD card, eMMC, and Ethernet all work there (where applicable).
</content>
</entry>
<entry>
<title>sunxi: pinctrl: Create the driver skeleton</title>
<updated>2022-04-04T22:23:50Z</updated>
<author>
<name>Samuel Holland</name>
<email>samuel@sholland.org</email>
</author>
<published>2021-08-13T01:09:43Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b799eabc7ee3086a708297d2309ebfe0be9adb68'/>
<id>urn:sha1:b799eabc7ee3086a708297d2309ebfe0be9adb68</id>
<content type='text'>
Create a do-nothing driver for each sunxi pin controller variant.

Since only one driver can automatically bind to a DT node, since the
GPIO driver already requires a manual binding process, and since the
pinctrl driver needs access to some of the same information, refactor
the GPIO driver to be bound by the pinctrl driver. This commit should
cause no functional change.

Signed-off-by: Samuel Holland &lt;samuel@sholland.org&gt;
Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'v2022.04-rc5' into next</title>
<updated>2022-03-28T16:36:49Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2022-03-28T16:36:49Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=34d2b7f20369d62c0f091d6572a8c0ea4655cf14'/>
<id>urn:sha1:34d2b7f20369d62c0f091d6572a8c0ea4655cf14</id>
<content type='text'>
Prepare v2022.04-rc5
</content>
</entry>
<entry>
<title>k210: use the board vendor name rather than the marketing name</title>
<updated>2022-03-15T09:43:11Z</updated>
<author>
<name>Damien Le Moal</name>
<email>damien.lemoal@opensource.wdc.com</email>
</author>
<published>2022-03-01T10:35:39Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=fd426b31066ba61ee1ff96a2b56c919251ffdd9e'/>
<id>urn:sha1:fd426b31066ba61ee1ff96a2b56c919251ffdd9e</id>
<content type='text'>
"kendryte" is the marketing name for the K210 RISC-V SoC produced by
Canaan Inc. Rather than "kendryte,k210", use the usual "canaan,k210"
vendor,SoC compatibility string format in the device tree files and
use the SoC name for file names.
With these changes, the device tree files are more in sync with the
Linux kernel DTS and drivers, making uboot device tree usable by the
kernel.

Signed-off-by: Damien Le Moal &lt;damien.lemoal@opensource.wdc.com&gt;
Signed-off-by: Niklas Cassel &lt;niklas.cassel@wdc.com&gt;
Reviewed-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
</content>
</entry>
<entry>
<title>pinctrl: zynqmp: Add pinctrl driver</title>
<updated>2022-03-14T14:23:31Z</updated>
<author>
<name>Ashok Reddy Soma</name>
<email>ashok.reddy.soma@xilinx.com</email>
</author>
<published>2022-02-23T14:23:05Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=dbd673f14da34148f5a6105a39cd4458a92cac67'/>
<id>urn:sha1:dbd673f14da34148f5a6105a39cd4458a92cac67</id>
<content type='text'>
Add pinctrl driver for Xilinx ZynqMP SOC. This driver is compatible with
linux device tree parameters for configuring pinmux and pinconf.

Signed-off-by: Ashok Reddy Soma &lt;ashok.reddy.soma@xilinx.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Link: https://lore.kernel.org/r/2d7eefa83c8c0129f7243a25de56a289e948f6c6.1645626183.git.michal.simek@xilinx.com
</content>
</entry>
<entry>
<title>pinctrl: Add Apple pinctrl driver</title>
<updated>2021-11-17T22:04:58Z</updated>
<author>
<name>Mark Kettenis</name>
<email>kettenis@openbsd.org</email>
</author>
<published>2021-11-02T17:21:57Z</published>
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<id>urn:sha1:b814e0007e060b5cce314edcf5c0507a67cafd73</id>
<content type='text'>
This driver supports both pin muxing and GPIO support for the
pin control logic found on Apple SoCs.

Signed-off-by: Mark Kettenis &lt;kettenis@openbsd.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: Add support for Kendryte K210 FPIOA</title>
<updated>2020-10-08T15:42:36Z</updated>
<author>
<name>Sean Anderson</name>
<email>seanga2@gmail.com</email>
</author>
<published>2020-09-14T15:01:58Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=7224d5ccf8e1d2552e2994c5d55769c334231c08'/>
<id>urn:sha1:7224d5ccf8e1d2552e2994c5d55769c334231c08</id>
<content type='text'>
The Fully-Programmable Input/Output Array (FPIOA) device controls pin
multiplexing on the K210. The FPIOA can remap any supported function to any
multifunctional IO pin. It can also perform basic GPIO functions, such as
reading the current value of a pin. However, GPIO functionality remains
largely unimplemented (in favor of the dedicated GPIO peripherals).

Signed-off-by: Sean Anderson &lt;seanga2@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
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