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<title>u-boot.git/drivers/pinctrl/aspeed/Makefile, branch main</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/pinctrl/aspeed/Makefile?h=main</id>
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<updated>2026-07-14T21:40:20Z</updated>
<entry>
<title>pinctrl: aspeed: Add AST2700 SoC1 pinctrl driver</title>
<updated>2026-07-14T21:40:20Z</updated>
<author>
<name>Billy Tsai</name>
<email>billy_tsai@aspeedtech.com</email>
</author>
<published>2026-07-02T10:08:36Z</published>
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<id>urn:sha1:c0e2aeb9dfe551a1b01a44dfffe917e8997898c3</id>
<content type='text'>
Add the pinctrl driver for the AST2700 SoC1 (I/O) die.

Unlike previous Aspeed generations, the SoC1 SCU assigns every pin a
4-bit multi-function selector field in a contiguous register range
starting at SCU 0x400, eight pins per register. Only bits [2:0] of
each field select the function; bit 3 is reserved read-only and must
not be written. The driver therefore keeps per-pin group tables and
per-function mux values, mirroring the Linux
aspeed,ast2700-soc1-pinctrl driver, and shares the same device tree
bindings: 220 pins, 238 groups and 217 functions with identical names,
so pin states written for the Linux driver work unmodified.

A few controls live outside the pin-indexed range and are handled as
virtual pins: PCIERC2_PERST (SCU 0x908), the USB2 port C/D mode fields
(SCU 0x3B0) and SGMII0 (SCU 0x47C).

The gpio_request_enable hook restores a pin to GPIO by writing mux
value 0, except for the ADC-capable balls W17..AB19 where function 1
selects GPIO and 0 selects the ADC input.

Signed-off-by: Billy Tsai &lt;billy_tsai@aspeedtech.com&gt;
</content>
</entry>
<entry>
<title>pinctrl: aspeed: Add AST2700 SoC0 pinctrl driver</title>
<updated>2026-07-14T21:40:20Z</updated>
<author>
<name>Billy Tsai</name>
<email>billy_tsai@aspeedtech.com</email>
</author>
<published>2026-07-02T10:08:34Z</published>
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<id>urn:sha1:1b87385aacf2c8a5d6d9296984509ae8376d6165</id>
<content type='text'>
The AST2700 is a dual-die BMC SoC: SoC0 (CPU die) and SoC1 (I/O die)
each have their own SCU with independent multi-function pin controls.

Add the pinctrl driver for the SoC0 die. The driver uses the generic
pinctrl framework and is compatible with the Linux kernel device tree
bindings, i.e. pin states are described with the same "function" and
"groups" properties and the same names as the Linux
aspeed,ast2700-soc0-pinctrl driver.

Unlike the older AST2500/AST2600 SCUs where each signal is enabled by
independent bits, the SoC0 mux selections mix single-bit enables
(eMMC, VGA DDC, VB strap), multi-bit selector fields (JTAG master port
select, USB2/USB3 port routing) and reset-control bits (PCIe RC
PERST). Model each (function, group) pair as one register
mask/value write so all of them fit a single flat table.

The gpio_request_enable hook releases the GPIO18A/GPIO18B pins to GPIO
mode by clearing every signal enable bit that claims the pin, matching
the Linux driver behaviour.

Signed-off-by: Billy Tsai &lt;billy_tsai@aspeedtech.com&gt;
</content>
</entry>
<entry>
<title>aspeed: AST2600 Pinctrl Driver</title>
<updated>2021-11-17T22:04:58Z</updated>
<author>
<name>Ryan Chen</name>
<email>ryan_chen@aspeedtech.com</email>
</author>
<published>2021-11-02T02:17:52Z</published>
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<id>urn:sha1:46220bf0174da71f49939633b3ebf00b8ed45b47</id>
<content type='text'>
This driver uses Pinctrl framework and is compatible with the Linux
driver for AST2600.

Signed-off-by: Ryan Chen &lt;ryan_chen@aspeedtech.com&gt;
Signed-off-by: Dylan Hung &lt;dylan_hung@aspeedtech.com&gt;
</content>
</entry>
<entry>
<title>aspeed: AST2500 Pinctrl Driver</title>
<updated>2017-05-08T15:57:33Z</updated>
<author>
<name>maxims@google.com</name>
<email>maxims@google.com</email>
</author>
<published>2017-04-17T19:00:27Z</published>
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<id>urn:sha1:4f0e44e46615e3c827dcd1ec59677be1058d394c</id>
<content type='text'>
This driver uses Generic Pinctrl framework and is compatible with
the Linux driver for ast2500: it uses the same device tree
configuration.

Not all pins are supported by the driver at the moment, so it actually
compatible with ast2400. In general, however, there are differences that
in the future would be easier to maintain separately.

Signed-off-by: Maxim Sloyko &lt;maxims@google.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
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