<feed xmlns='http://www.w3.org/2005/Atom'>
<title>u-boot.git/drivers/pinctrl/aspeed, branch main</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/pinctrl/aspeed?h=main</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/pinctrl/aspeed?h=main'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2026-07-14T21:40:20Z</updated>
<entry>
<title>pinctrl: aspeed: Add AST2700 SoC1 pinconf support</title>
<updated>2026-07-14T21:40:20Z</updated>
<author>
<name>Billy Tsai</name>
<email>billy_tsai@aspeedtech.com</email>
</author>
<published>2026-07-02T10:08:37Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=02d74afe94a5510312d01ad79a3801c589cb6a20'/>
<id>urn:sha1:02d74afe94a5510312d01ad79a3801c589cb6a20</id>
<content type='text'>
The SoC1 SCU provides a bias enable bit per pin in the registers at
0x480 (setting the bit disables the bias; the pull direction is fixed
in silicon) and 2-bit drive strength fields at 0x4C0 selecting 4 mA to
16 mA in 4 mA steps. The pin-to-field mapping of the drive strength
registers is sparse and non-linear, so it is kept in a lookup table
mirroring the Linux driver; pins without an entry reject
drive-strength with -ENOTSUPP.

Support the bias-disable, bias-pull-down, bias-pull-up and
drive-strength properties per pin and per group, and select PINCONF so
the generic pinctrl framework parses them.

Signed-off-by: Billy Tsai &lt;billy_tsai@aspeedtech.com&gt;
</content>
</entry>
<entry>
<title>pinctrl: aspeed: Add AST2700 SoC1 pinctrl driver</title>
<updated>2026-07-14T21:40:20Z</updated>
<author>
<name>Billy Tsai</name>
<email>billy_tsai@aspeedtech.com</email>
</author>
<published>2026-07-02T10:08:36Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c0e2aeb9dfe551a1b01a44dfffe917e8997898c3'/>
<id>urn:sha1:c0e2aeb9dfe551a1b01a44dfffe917e8997898c3</id>
<content type='text'>
Add the pinctrl driver for the AST2700 SoC1 (I/O) die.

Unlike previous Aspeed generations, the SoC1 SCU assigns every pin a
4-bit multi-function selector field in a contiguous register range
starting at SCU 0x400, eight pins per register. Only bits [2:0] of
each field select the function; bit 3 is reserved read-only and must
not be written. The driver therefore keeps per-pin group tables and
per-function mux values, mirroring the Linux
aspeed,ast2700-soc1-pinctrl driver, and shares the same device tree
bindings: 220 pins, 238 groups and 217 functions with identical names,
so pin states written for the Linux driver work unmodified.

A few controls live outside the pin-indexed range and are handled as
virtual pins: PCIERC2_PERST (SCU 0x908), the USB2 port C/D mode fields
(SCU 0x3B0) and SGMII0 (SCU 0x47C).

The gpio_request_enable hook restores a pin to GPIO by writing mux
value 0, except for the ADC-capable balls W17..AB19 where function 1
selects GPIO and 0 selects the ADC input.

Signed-off-by: Billy Tsai &lt;billy_tsai@aspeedtech.com&gt;
</content>
</entry>
<entry>
<title>pinctrl: aspeed: Add AST2700 SoC0 pinconf support</title>
<updated>2026-07-14T21:40:20Z</updated>
<author>
<name>Billy Tsai</name>
<email>billy_tsai@aspeedtech.com</email>
</author>
<published>2026-07-02T10:08:35Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ada5d0e7e2ceb118a70df7d8c15b53d0d91c7d3b'/>
<id>urn:sha1:ada5d0e7e2ceb118a70df7d8c15b53d0d91c7d3b</id>
<content type='text'>
Each GPIO18A/GPIO18B ball has its own IO control register starting at
SCU 0x480, providing a 4-bit drive strength selector (3 mA to 41 mA in
hardware-defined steps), a bias enable bit and a pull direction bit.

Extend the group table with the pin members of the ball-backed groups
so bias-disable, bias-pull-down, bias-pull-up and drive-strength
properties can be applied per group as well as per pin. The routing
groups (USB, JTAG, PCIe RC) have no package balls and reject pin
configuration with -ENOTSUPP.

Select PINCONF so the generic pinctrl framework parses the pin
configuration properties.

Signed-off-by: Billy Tsai &lt;billy_tsai@aspeedtech.com&gt;
</content>
</entry>
<entry>
<title>pinctrl: aspeed: Add AST2700 SoC0 pinctrl driver</title>
<updated>2026-07-14T21:40:20Z</updated>
<author>
<name>Billy Tsai</name>
<email>billy_tsai@aspeedtech.com</email>
</author>
<published>2026-07-02T10:08:34Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1b87385aacf2c8a5d6d9296984509ae8376d6165'/>
<id>urn:sha1:1b87385aacf2c8a5d6d9296984509ae8376d6165</id>
<content type='text'>
The AST2700 is a dual-die BMC SoC: SoC0 (CPU die) and SoC1 (I/O die)
each have their own SCU with independent multi-function pin controls.

Add the pinctrl driver for the SoC0 die. The driver uses the generic
pinctrl framework and is compatible with the Linux kernel device tree
bindings, i.e. pin states are described with the same "function" and
"groups" properties and the same names as the Linux
aspeed,ast2700-soc0-pinctrl driver.

Unlike the older AST2500/AST2600 SCUs where each signal is enabled by
independent bits, the SoC0 mux selections mix single-bit enables
(eMMC, VGA DDC, VB strap), multi-bit selector fields (JTAG master port
select, USB2/USB3 port routing) and reset-control bits (PCIe RC
PERST). Model each (function, group) pair as one register
mask/value write so all of them fit a single flat table.

The gpio_request_enable hook releases the GPIO18A/GPIO18B pins to GPIO
mode by clearing every signal enable bit that claims the pin, matching
the Linux driver behaviour.

Signed-off-by: Billy Tsai &lt;billy_tsai@aspeedtech.com&gt;
</content>
</entry>
<entry>
<title>ARM: dts: ast2600: Add SGPIO to device tree</title>
<updated>2024-10-29T18:12:04Z</updated>
<author>
<name>Billy Tsai</name>
<email>billy_tsai@aspeedtech.com</email>
</author>
<published>2024-10-16T08:59:55Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=4d5510774d4905f1966388098cf918ca27118197'/>
<id>urn:sha1:4d5510774d4905f1966388098cf918ca27118197</id>
<content type='text'>
Add SGPIO DTS node and enable them for AST2600 EVB.

Signed-off-by: Billy Tsai &lt;billy_tsai@aspeedtech.com&gt;
</content>
</entry>
<entry>
<title>ARM: dts: ast2500: Add SGPIO to device tree</title>
<updated>2024-10-29T18:12:04Z</updated>
<author>
<name>Billy Tsai</name>
<email>billy_tsai@aspeedtech.com</email>
</author>
<published>2024-10-16T08:59:54Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=be298254bee70b4914f9630e04dc5a8968b0d0fc'/>
<id>urn:sha1:be298254bee70b4914f9630e04dc5a8968b0d0fc</id>
<content type='text'>
Add SGPIO DTS node and enable it for AST2500 EVB.

Signed-off-by: Billy Tsai &lt;billy_tsai@aspeedtech.com&gt;
</content>
</entry>
<entry>
<title>Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"</title>
<updated>2024-05-20T19:35:03Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-05-20T19:35:03Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=03de305ec48b0bb28554372abb40ccd46dbe0bf9'/>
<id>urn:sha1:03de305ec48b0bb28554372abb40ccd46dbe0bf9</id>
<content type='text'>
As part of bringing the master branch back in to next, we need to allow
for all of these changes to exist here.

Reported-by: Jonas Karlman &lt;jonas@kwiboo.se&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""</title>
<updated>2024-05-19T14:16:36Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-05-19T02:20:43Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d678a59d2d719da9e807495b4b021501f2836ca5'/>
<id>urn:sha1:d678a59d2d719da9e807495b4b021501f2836ca5</id>
<content type='text'>
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay
Ethernet"' I failed to notice that b4 noticed it was based on next and
so took that as the base commit and merged that part of next to master.

This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing
changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35.

Reported-by: Jonas Karlman &lt;jonas@kwiboo.se&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>pinctrl: Remove &lt;common.h&gt; and add needed includes</title>
<updated>2024-05-07T14:00:56Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-05-02T01:31:08Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c45973bc60f319de2737618400883023f2b648da'/>
<id>urn:sha1:c45973bc60f319de2737618400883023f2b648da</id>
<content type='text'>
Remove &lt;common.h&gt; from this driver directory and when needed
add missing include files directly.

Reviewed-by: Peter Robinson &lt;pbrobinson@gmail.com&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>pinctrl: aspeed: add pass-through pins and siopbi/siopbo</title>
<updated>2024-03-01T21:35:52Z</updated>
<author>
<name>Ivan Mikhaylov</name>
<email>fr0st61te@gmail.com</email>
</author>
<published>2024-01-20T23:28:13Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=88bb4104adab6d92084297c73a685468325d28a9'/>
<id>urn:sha1:88bb4104adab6d92084297c73a685468325d28a9</id>
<content type='text'>
Add THRU0-3 and SIOPBI/SIOPBO pin groups/functions.

Signed-off-by: Ivan Mikhaylov &lt;fr0st61te@gmail.com&gt;
</content>
</entry>
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