u-boot.git/drivers/pinctrl/mscc, branch v2020.04 Unnamed repository; edit this file 'description' to name the repository. dm: core: Create a new header file for 'compat' features 2020-02-06T02:33:46+00:00 Simon Glass sjg@chromium.org 2020-02-03T14:36:16+00:00 336d4615f8fa774557d14f9b3245daa9e5fe3dbc At present dm/device.h includes the linux-compatible features. This requires including linux/compat.h which in turn includes a lot of headers. One of these is malloc.h which we thus end up including in every file in U-Boot. Apart from the inefficiency of this, it is problematic for sandbox which needs to use the system malloc() in some files. Move the compatibility features into a separate header file. Signed-off-by: Simon Glass <sjg@chromium.org> 
At present dm/device.h includes the linux-compatible features. This
requires including linux/compat.h which in turn includes a lot of headers.
One of these is malloc.h which we thus end up including in every file in
U-Boot. Apart from the inefficiency of this, it is problematic for sandbox
which needs to use the system malloc() in some files.

Move the compatibility features into a separate header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
dm: core: Require users of devres to include the header 2020-02-06T02:33:46+00:00 Simon Glass sjg@chromium.org 2020-02-03T14:36:15+00:00 61b29b82683863a970fd4609a7c58512872616bc At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de> 
At present devres.h is included in all files that include dm.h but few
make use of it. Also this pulls in linux/compat which adds several more
headers. Drop the automatic inclusion and require files to include devres
themselves. This provides a good indication of which files use devres.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
pinctrl: mscc: Add gpio and pinctrl for Serval SoC family. 2019-01-23T17:28:09+00:00 Horatiu Vultur horatiu.vultur@microchip.com 2019-01-23T15:39:41+00:00 5c31ce36e33d6e6216bfa56d176976eca017afb6 The Serval SoC family has 32 pins. Currently there is no support for Serval in Linux kernel. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> 
The Serval SoC family has 32 pins. Currently there is no
support for Serval in Linux kernel.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
pinctrl: mscc: Add gpio and pinctrl for Servalt SoC family. 2019-01-23T17:27:26+00:00 Horatiu Vultur horatiu.vultur@microchip.com 2019-01-17T14:33:26+00:00 177c07f8293f510eaa3d802eae58c7ed0d664337 The Servalt SoC family has 36 pins. Currently there is not support for Servalt pinctrl in Linux kernel. Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> 
The Servalt SoC family has 36 pins. Currently there is not support
for Servalt pinctrl in Linux kernel.

Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
pinctrl: mscc: Add gpio and pinctrl for Jaguar2 SOC family 2019-01-16T12:56:43+00:00 Horatiu Vultur horatiu.vultur@microchip.com 2019-01-12T17:56:55+00:00 051de9b3eb445107b497dd9d92382f8cfa2781a1 The Jaguar2 SOC family has 63 gpio pins therefore I extended mscc-common to support new numbe of pins and remove any platform dependency from mscc-common. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> 
The Jaguar2 SOC family has 63 gpio pins therefore I extended mscc-common
to support new numbe of pins and remove any platform dependency from
mscc-common.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
pinctrl: mscc: Add gpio and pinctrl driver for MSCC MIPS SoCs (VcoreIII based) 2018-12-19T14:23:01+00:00 Gregory CLEMENT gregory.clement@bootlin.com 2018-12-08T08:59:01+00:00 53bdae241888de3d23a51735e9610389921b80ae This driver supports the pin and gpio controller found in the Ocelot and Luton SoCs. The driver was inspired from the pinctrl driver in Linux, but was simplified and was modified to allow supporting an other SoCs (Luton). For Ocelot and Luton the controller is the same, only the pins to program differ. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> [changed to only descend into mscc/ dependent on CONFIG_PINCTRL_MSCC] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> 
This driver supports the pin and gpio controller found in the Ocelot and
Luton SoCs.

The driver was inspired from the pinctrl driver in Linux, but was
simplified and was modified to allow supporting an other SoCs (Luton).

For Ocelot and Luton the controller is the same, only the pins to program
differ.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
[changed to only descend into mscc/ dependent on CONFIG_PINCTRL_MSCC]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>