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<title>u-boot.git/drivers/pinctrl/mvebu, branch v2018.05</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers/pinctrl/mvebu?h=v2018.05</id>
<link rel='self' href='http://cgit.235523.xyz/u-boot.git/atom/drivers/pinctrl/mvebu?h=v2018.05'/>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<updated>2018-05-07T13:34:12Z</updated>
<entry>
<title>SPDX: Convert all of our single license tags to Linux Kernel style</title>
<updated>2018-05-07T13:34:12Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-05-06T21:58:06Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=83d290c56fab2d38cd1ab4c4cc7099559c1d5046'/>
<id>urn:sha1:83d290c56fab2d38cd1ab4c4cc7099559c1d5046</id>
<content type='text'>
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>arm64: a37xx: pinctrl: Correct mpp definitions</title>
<updated>2018-03-30T10:52:48Z</updated>
<author>
<name>Ken Ma</name>
<email>make@marvell.com</email>
</author>
<published>2018-03-26T07:56:03Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=dc36235abe408cf450daa7b06d612084119dd841'/>
<id>urn:sha1:dc36235abe408cf450daa7b06d612084119dd841</id>
<content type='text'>
This patch corrects below mpp definitions:
 - The sdio_sb group is composed of 6 pins and not 5;
 - The rgmii group contains pins mpp2[17:6] and not mpp2[19:6];
 - Pin of group "pmic0" is mpp1[6] but not mpp1[16];
 - Pin of group "pmic1" is mpp1[7] but not mpp1[17];
 - A new group "smi" is added in A0 with 2 pins - mpp2[19:18], its
   bitmask is bit4;
 - Group "pcie1" has 3 pins in A0 - mpp2[5:3], its bit mask is
   bit5 | bit9 | bit10 but not bit4;
 - Group "ptp" has 3 pins in A0 as Z1, but its bitmask is changed to
   bit11 | bit12 | bit13.

Reviewed-on: http://vgitil04.il.marvell.com:8080/43288
Tested-by: iSoC Platform CI &lt;ykjenk@marvell.com&gt;
Reviewed-by: Hua Jing &lt;jinghua@marvell.com&gt;
Cc: Simon Glass &lt;sjg@chromium.org&gt;
Cc: Stefan Roese &lt;sr@denx.de&gt;
Signed-off-by: Ken Ma &lt;make@marvell.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>arm64: a37xx: pinctrl: Fix gpio pin offset in register</title>
<updated>2018-03-30T10:52:48Z</updated>
<author>
<name>Ken Ma</name>
<email>make@marvell.com</email>
</author>
<published>2018-03-26T07:56:02Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=0237448a715468f910d2b30c548c171380f901c1'/>
<id>urn:sha1:0237448a715468f910d2b30c548c171380f901c1</id>
<content type='text'>
For armada_37xx_update_reg(), the parameter offset should be pointer so
that it can be updated, otherwise offset will keep old value, and then
when offset is larger than or equal to 32 the mask calculated by
"BIT(offset)" will be 0 in gpio chip hook functions, it's an error,
this patch set offset parameter of armada_37xx_update_reg() as pointer.

Reviewed-on: http://vgitil04.il.marvell.com:8080/43287
Reviewed-by: Hua Jing &lt;jinghua@marvell.com&gt;
Tested-by: iSoC Platform CI &lt;ykjenk@marvell.com&gt;
Cc: Simon Glass &lt;sjg@chromium.org&gt;
Cc: Stefan Roese &lt;sr@denx.de&gt;
Signed-off-by: Ken Ma &lt;make@marvell.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>arm64: a37xx: pinctrl: Fix the pin 23 on south bridge</title>
<updated>2018-03-30T10:52:48Z</updated>
<author>
<name>Ken Ma</name>
<email>make@marvell.com</email>
</author>
<published>2018-03-26T07:56:01Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=23626cac4b8a2a4a95b109526a97b3916ae2a40e'/>
<id>urn:sha1:23626cac4b8a2a4a95b109526a97b3916ae2a40e</id>
<content type='text'>
Pin 23 on South bridge does not belong to the rgmii group. It belongs to
a separate group which can have 3 functions.

Due to this the fix also have to update the way the functions are
managed. Until now each groups used NB_FUNCS(which was 2) functions. For
the mpp23, 3 functions are available but it is the only group which needs
it, so on the loop involving NB_FUNCS an extra test was added to handle
only the functions added.

The bug was visible when the gpio regulator used the gpio 23, the whole
rgmii group was setup to gpio which broke the Ethernet support on the
Armada 3720 DB board. Thanks to this patch, the UHS SD cards (which need
the vqmmc) _and_ the Ethernet work again.

Reviewed-on: http://vgitil04.il.marvell.com:8080/43284
Reviewed-by: Hua Jing &lt;jinghua@marvell.com&gt;
Tested-by: iSoC Platform CI &lt;ykjenk@marvell.com&gt;
Cc: Simon Glass &lt;sjg@chromium.org&gt;
Cc: Stefan Roese &lt;sr@denx.de&gt;
Signed-off-by: Ken Ma &lt;make@marvell.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>arm64: a37xx: pinctrl: Fix number of pin in south bridge</title>
<updated>2018-03-30T10:52:48Z</updated>
<author>
<name>Ken Ma</name>
<email>make@marvell.com</email>
</author>
<published>2018-03-26T07:55:59Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=44ac747bdfceeefdf3cd70caed05eddfe23affb8'/>
<id>urn:sha1:44ac747bdfceeefdf3cd70caed05eddfe23affb8</id>
<content type='text'>
On the south bridge we have pin from 0 to 29, so it gives 30 pins (and
not 29).

Reviewed-on: http://vgitil04.il.marvell.com:8080/43285
Tested-by: iSoC Platform CI &lt;ykjenk@marvell.com&gt;
Reviewed-by: Hua Jing &lt;jinghua@marvell.com&gt;
Cc: Simon Glass &lt;sjg@chromium.org&gt;
Cc: Stefan Roese &lt;sr@denx.de&gt;
Signed-off-by: Ken Ma &lt;make@marvell.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>pinctrl: mvebu: Make drivers depend on the pinctrl framework</title>
<updated>2018-01-09T15:41:00Z</updated>
<author>
<name>Miquel Raynal</name>
<email>miquel.raynal@free-electrons.com</email>
</author>
<published>2017-12-29T14:31:56Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3f3946d30daf9a2dc66d03c6b2b3959ffb18ac40'/>
<id>urn:sha1:3f3946d30daf9a2dc66d03c6b2b3959ffb18ac40</id>
<content type='text'>
Armada pinctrl drivers shall not be compiled without the entire pinctrl
framework and thus lack a "depends on" condition, otherwise the driver
will simply not be probed.

Signed-off-by: Miquel Raynal &lt;miquel.raynal@free-electrons.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>treewide: replace with error() with pr_err()</title>
<updated>2017-10-04T15:59:44Z</updated>
<author>
<name>Masahiro Yamada</name>
<email>yamada.masahiro@socionext.com</email>
</author>
<published>2017-09-16T05:10:41Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=9b643e312d528f291966c1f30b0d90bf3b1d43dc'/>
<id>urn:sha1:9b643e312d528f291966c1f30b0d90bf3b1d43dc</id>
<content type='text'>
U-Boot widely uses error() as a bit noisier variant of printf().

This macro causes name conflict with the following line in
include/linux/compiler-gcc.h:

  # define __compiletime_error(message) __attribute__((error(message)))

This prevents us from using __compiletime_error(), and makes it
difficult to fully sync BUILD_BUG macros with Linux.  (Notice
Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().)

Let's convert error() into now treewide-available pr_err().

Done with the help of Coccinelle, excluing tools/ directory.

The semantic patch I used is as follows:

// &lt;smpl&gt;
@@@@
-error
+pr_err
 (...)
// &lt;/smpl&gt;

Signed-off-by: Masahiro Yamada &lt;yamada.masahiro@socionext.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
[trini: Re-run Coccinelle]
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>pinctrl: a3700: Fix the issue that gpio controller is registered with wrong node id</title>
<updated>2017-06-23T05:09:40Z</updated>
<author>
<name>Ken Ma</name>
<email>make@marvell.com</email>
</author>
<published>2017-06-22T09:13:36Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ae118b6855a7d003a7d024129e686c8a4a400141'/>
<id>urn:sha1:ae118b6855a7d003a7d024129e686c8a4a400141</id>
<content type='text'>
In armada_37xx_gpiochip_register, the return value of fdtdec_get_bool
should be true when gpio-controller is found; current codes makes a
wrong inverse return value judgement, this patch fixes it.

Signed-off-by: Ken Ma &lt;make@marvell.com&gt;
Cc: Stefan Roese &lt;sr@denx.de&gt;
Cc: Kostya Porotchkin &lt;kostap@marvell.com&gt;
Cc: Gregory CLEMENT &lt;gregory.clement@free-electrons.com&gt;
Cc: Nadav Haklai &lt;nadavh@marvell.com&gt;
Cc: Wilson Ding &lt;dingwei@marvell.com&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>pinctrl: a3700: Fix uart2 group selection register mask</title>
<updated>2017-06-23T05:09:40Z</updated>
<author>
<name>Ken Ma</name>
<email>make@marvell.com</email>
</author>
<published>2017-06-22T09:13:35Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b5a6c94a0380071600dc5b8be1853164f62af146'/>
<id>urn:sha1:b5a6c94a0380071600dc5b8be1853164f62af146</id>
<content type='text'>
If north bridge selection register bit1 is clear, pins [10:8] are for
SDIO0 Resetn, Wakeup, and PDN while if bit1 is set, pins [10:8]are for
GPIO; when bit1 is clear, pin 9 and pin 10 can be used for uart2 RTSn
and CTSn, so bit1 should be added to uart2 group and it must be set
for both "gpio" and "uart" functions of uart2 group.

Signed-off-by: Ken Ma &lt;make@marvell.com&gt;
Cc: Stefan Roese &lt;sr@denx.de&gt;
Cc: Kostya Porotchkin &lt;kostap@marvell.com&gt;
Cc: Gregory CLEMENT &lt;gregory.clement@free-electrons.com&gt;
Cc: Nadav Haklai &lt;nadavh@marvell.com&gt;
Cc: Wilson Ding &lt;dingwei@marvell.com&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>dm: Rename dev_addr..() functions</title>
<updated>2017-06-01T13:03:01Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2017-05-17T23:18:05Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a821c4af79e4f5ce9b629b20473863397bbe9b10'/>
<id>urn:sha1:a821c4af79e4f5ce9b629b20473863397bbe9b10</id>
<content type='text'>
These support the flat device tree. We want to use the dev_read_..()
prefix for functions that support both flat tree and live tree. So rename
the existing functions to avoid confusion.

In the end we will have:

   1. dev_read_addr...()    - works on devices, supports flat/live tree
   2. devfdt_get_addr...()  - current functions, flat tree only
   3. of_get_address() etc. - new functions, live tree only

All drivers will be written to use 1. That function will in turn call
either 2 or 3 depending on whether the flat or live tree is in use.

Note this involves changing some dead code - the imx_lpi2c.c file.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
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