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<title>u-boot.git/drivers/pinctrl/qcom, branch next</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>pinctrl: qcom: add PINCTRL_QCOM_GENERIC to enable all drivers by default</title>
<updated>2026-01-14T15:25:09+00:00</updated>
<author>
<name>Aswin Murugan</name>
<email>aswin.murugan@oss.qualcomm.com</email>
</author>
<published>2026-01-07T15:47:44+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=25a260c2cbcc3fadb1059f9b20e38e06038ccf4b'/>
<id>25a260c2cbcc3fadb1059f9b20e38e06038ccf4b</id>
<content type='text'>
Introduce a new Kconfig option PINCTRL_QCOM_GENERIC that, when selected,
enables all Qualcomm pinctrl drivers by default. This simplifies defconfigs
for platforms supporting multiple SoCs and avoids manual driver selection.
Individual drivers can still be disabled if required.

Signed-off-by: Aswin Murugan &lt;aswin.murugan@oss.qualcomm.com&gt;
Reviewed-by: Casey Connolly &lt;casey.connolly@linaro.org&gt;
Link: https://patch.msgid.link/20260107154745.571319-2-aswin.murugan@oss.qualcomm.com
Signed-off-by: Casey Connolly &lt;casey.connolly@linaro.org&gt;
</content>
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<pre>
Introduce a new Kconfig option PINCTRL_QCOM_GENERIC that, when selected,
enables all Qualcomm pinctrl drivers by default. This simplifies defconfigs
for platforms supporting multiple SoCs and avoids manual driver selection.
Individual drivers can still be disabled if required.

Signed-off-by: Aswin Murugan &lt;aswin.murugan@oss.qualcomm.com&gt;
Reviewed-by: Casey Connolly &lt;casey.connolly@linaro.org&gt;
Link: https://patch.msgid.link/20260107154745.571319-2-aswin.murugan@oss.qualcomm.com
Signed-off-by: Casey Connolly &lt;casey.connolly@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pinctrl: qcom: add driver for QCS615 SoC</title>
<updated>2026-01-14T15:25:09+00:00</updated>
<author>
<name>Aswin Murugan</name>
<email>aswin.murugan@oss.qualcomm.com</email>
</author>
<published>2025-11-12T16:47:57+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=46a66c02e9d5211f9c5b2380246680e6bfb31ff5'/>
<id>46a66c02e9d5211f9c5b2380246680e6bfb31ff5</id>
<content type='text'>
Add pinctrl driver for QCS615. Driver code is based on the
similar U-Boot and Linux drivers.

Signed-off-by: Aswin Murugan &lt;aswin.murugan@oss.qualcomm.com&gt;
Reviewed-by: Neil Armstrong &lt;neil.armstrong@linaro.org&gt;
Link: https://patch.msgid.link/20251112164758.1560041-2-aswin.murugan@oss.qualcomm.com
Signed-off-by: Casey Connolly &lt;casey.connolly@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add pinctrl driver for QCS615. Driver code is based on the
similar U-Boot and Linux drivers.

Signed-off-by: Aswin Murugan &lt;aswin.murugan@oss.qualcomm.com&gt;
Reviewed-by: Neil Armstrong &lt;neil.armstrong@linaro.org&gt;
Link: https://patch.msgid.link/20251112164758.1560041-2-aswin.murugan@oss.qualcomm.com
Signed-off-by: Casey Connolly &lt;casey.connolly@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pinctrl: qcom: add SM7150 pinctrl driver</title>
<updated>2025-10-29T11:27:33+00:00</updated>
<author>
<name>Danila Tikhonov</name>
<email>danila@jiaxyga.com</email>
</author>
<published>2025-08-31T00:46:00+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=23fc229eb422cb48c0786869cb90bd3f2b24839b'/>
<id>23fc229eb422cb48c0786869cb90bd3f2b24839b</id>
<content type='text'>
This SoC features a pinctrl block with north, south, and west tiles
accessible to the AP.

Signed-off-by: Danila Tikhonov &lt;danila@jiaxyga.com&gt;
Co-developed-by: Jens Reidel &lt;adrian@mainlining.org&gt;
Signed-off-by: Jens Reidel &lt;adrian@mainlining.org&gt;
Link: https://lore.kernel.org/r/20250831004602.699953-3-adrian@mainlining.org
Signed-off-by: Casey Connolly &lt;kcxt@postmarketos.org&gt;
</content>
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<pre>
This SoC features a pinctrl block with north, south, and west tiles
accessible to the AP.

Signed-off-by: Danila Tikhonov &lt;danila@jiaxyga.com&gt;
Co-developed-by: Jens Reidel &lt;adrian@mainlining.org&gt;
Signed-off-by: Jens Reidel &lt;adrian@mainlining.org&gt;
Link: https://lore.kernel.org/r/20250831004602.699953-3-adrian@mainlining.org
Signed-off-by: Casey Connolly &lt;kcxt@postmarketos.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drivers: pinctrl: Add Qualcomm SM6350 TLMM driver</title>
<updated>2025-10-29T11:27:33+00:00</updated>
<author>
<name>Luca Weiss</name>
<email>luca.weiss@fairphone.com</email>
</author>
<published>2025-09-17T12:47:36+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5af87d808841bfa48242deae4d86b7858d36479b'/>
<id>5af87d808841bfa48242deae4d86b7858d36479b</id>
<content type='text'>
Add support for TLMM pin controller block (Top Level Mode Multiplexer)
on SM6350 SoC, with support for special pins.

Correct pin configuration is required for working debug UART and eMMC/SD
cards.

Reviewed-by: Neil Armstrong &lt;neil.armstrong@linaro.org&gt;
Signed-off-by: Luca Weiss &lt;luca.weiss@fairphone.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add support for TLMM pin controller block (Top Level Mode Multiplexer)
on SM6350 SoC, with support for special pins.

Correct pin configuration is required for working debug UART and eMMC/SD
cards.

Reviewed-by: Neil Armstrong &lt;neil.armstrong@linaro.org&gt;
Signed-off-by: Luca Weiss &lt;luca.weiss@fairphone.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pinctrl: qcom: sc7280: Fix offset of UFS_RESET</title>
<updated>2025-10-29T11:27:33+00:00</updated>
<author>
<name>Luca Weiss</name>
<email>luca.weiss@fairphone.com</email>
</author>
<published>2025-09-24T11:30:07+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e4b35d364e8639160d3ab2d73b3c53cc4ab69880'/>
<id>e4b35d364e8639160d3ab2d73b3c53cc4ab69880</id>
<content type='text'>
There's no WEST, SOUTH or NORTH in sc7280 pinctrl. Fix the offset of the
ufs_reset pin.

Fixes: 51ec7fdb64b ("pinctrl: qcom: add sc7280 pinctrl driver")
Signed-off-by: Luca Weiss &lt;luca.weiss@fairphone.com&gt;
Reviewed-by: Neil Armstrong &lt;neil.armstrong@linaro.org&gt;
Link: https://lore.kernel.org/r/20250924-2025-10-misc-v1-1-7e75842ca714@fairphone.com
Signed-off-by: Casey Connolly &lt;kcxt@postmarketos.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
There's no WEST, SOUTH or NORTH in sc7280 pinctrl. Fix the offset of the
ufs_reset pin.

Fixes: 51ec7fdb64b ("pinctrl: qcom: add sc7280 pinctrl driver")
Signed-off-by: Luca Weiss &lt;luca.weiss@fairphone.com&gt;
Reviewed-by: Neil Armstrong &lt;neil.armstrong@linaro.org&gt;
Link: https://lore.kernel.org/r/20250924-2025-10-misc-v1-1-7e75842ca714@fairphone.com
Signed-off-by: Casey Connolly &lt;kcxt@postmarketos.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pinctrl: qcom: add sdm670 pinctrl driver</title>
<updated>2025-10-29T11:27:32+00:00</updated>
<author>
<name>David Wronek</name>
<email>david.wronek@mainlining.org</email>
</author>
<published>2025-10-03T10:01:11+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f977cee37252c6f1d215f76c2905cd8823b03fdb'/>
<id>f977cee37252c6f1d215f76c2905cd8823b03fdb</id>
<content type='text'>
Add a pinctrl driver for the TLMM block found in the SDM670 SoC.

Signed-off-by: David Wronek &lt;david.wronek@mainlining.org&gt;
Link: https://lore.kernel.org/r/20251003-sdm670-v2-3-52c0fa481286@mainlining.org
Signed-off-by: Casey Connolly &lt;kcxt@postmarketos.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add a pinctrl driver for the TLMM block found in the SDM670 SoC.

Signed-off-by: David Wronek &lt;david.wronek@mainlining.org&gt;
Link: https://lore.kernel.org/r/20251003-sdm670-v2-3-52c0fa481286@mainlining.org
Signed-off-by: Casey Connolly &lt;kcxt@postmarketos.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pinctrl: qcom: sdm845: Limit check off by 1</title>
<updated>2025-08-13T13:18:49+00:00</updated>
<author>
<name>Andrew Goodbody</name>
<email>andrew.goodbody@linaro.org</email>
</author>
<published>2025-08-07T11:20:02+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d9fbc1d70bc9d5e7665c9fc1ed71d25e04faba54'/>
<id>d9fbc1d70bc9d5e7665c9fc1ed71d25e04faba54</id>
<content type='text'>
The driver specifies 154 pins so should have a maximum selector of 153
to ensure that the index into the array special_pins_names does not
overflow.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody &lt;andrew.goodbody@linaro.org&gt;
Link: https://lore.kernel.org/r/20250807-pinctrl_qcom-v1-2-42fac6707fd5@linaro.org
Signed-off-by: Casey Connolly &lt;casey.connolly@linaro.org&gt;
</content>
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<pre>
The driver specifies 154 pins so should have a maximum selector of 153
to ensure that the index into the array special_pins_names does not
overflow.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody &lt;andrew.goodbody@linaro.org&gt;
Link: https://lore.kernel.org/r/20250807-pinctrl_qcom-v1-2-42fac6707fd5@linaro.org
Signed-off-by: Casey Connolly &lt;casey.connolly@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pinctrl: qcom: sa8775: Limit check for array index not correct</title>
<updated>2025-08-13T13:18:49+00:00</updated>
<author>
<name>Andrew Goodbody</name>
<email>andrew.goodbody@linaro.org</email>
</author>
<published>2025-08-07T11:20:01+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=be12b6e158a06580437f2e4756eb6021cf0cbfbe'/>
<id>be12b6e158a06580437f2e4756eb6021cf0cbfbe</id>
<content type='text'>
In sa8775p_get_pin_name the limit check for the index into
msm_special_pins_data allows for more elements than exist. Add code to
ensure the array index remains in bounds.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody &lt;andrew.goodbody@linaro.org&gt;
Link: https://lore.kernel.org/r/20250807-pinctrl_qcom-v1-1-42fac6707fd5@linaro.org
Signed-off-by: Casey Connolly &lt;casey.connolly@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
In sa8775p_get_pin_name the limit check for the index into
msm_special_pins_data allows for more elements than exist. Add code to
ensure the array index remains in bounds.

This issue was found by Smatch.

Signed-off-by: Andrew Goodbody &lt;andrew.goodbody@linaro.org&gt;
Link: https://lore.kernel.org/r/20250807-pinctrl_qcom-v1-1-42fac6707fd5@linaro.org
Signed-off-by: Casey Connolly &lt;casey.connolly@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pinctrl: qcom: Add ipq5424 pinctrl driver</title>
<updated>2025-06-23T16:50:21+00:00</updated>
<author>
<name>Varadarajan Narayanan</name>
<email>quic_varada@quicinc.com</email>
</author>
<published>2025-03-04T11:01:04+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c4aa86c04f59a79cbfe938bd32cc676d48a083d3'/>
<id>c4aa86c04f59a79cbfe938bd32cc676d48a083d3</id>
<content type='text'>
Add pinctrl driver for the TLMM block found in the ipq5424 SoC.

Signed-off-by: Varadarajan Narayanan &lt;quic_varada@quicinc.com&gt;
Reviewed-by: Casey Connolly &lt;casey.connolly@linaro.org&gt;
Link: https://lore.kernel.org/r/20250304110105.2762124-6-quic_varada@quicinc.com
Signed-off-by: Casey Connolly &lt;casey.connolly@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add pinctrl driver for the TLMM block found in the ipq5424 SoC.

Signed-off-by: Varadarajan Narayanan &lt;quic_varada@quicinc.com&gt;
Reviewed-by: Casey Connolly &lt;casey.connolly@linaro.org&gt;
Link: https://lore.kernel.org/r/20250304110105.2762124-6-quic_varada@quicinc.com
Signed-off-by: Casey Connolly &lt;casey.connolly@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge patch series "Qualcomm: cleanup OF_LIVE fixup and fix RB1/2"</title>
<updated>2025-05-02T14:38:27+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2025-05-02T14:38:27+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=4ca87fd18c1b718be423755939a6e5b1688869f5'/>
<id>4ca87fd18c1b718be423755939a6e5b1688869f5</id>
<content type='text'>
Caleb Connolly &lt;caleb.connolly@linaro.org&gt; says:

Introduce a new event to signal that the live tree has been built,
allowing boards to perform fixups on the tree before devices are bound.
Crucially this allows for devices to be enabled or disabled, but also
allows for properties that are parsed during the bind stage to be
modified (such as dr_mode for dwc3).

With this in place, mach-snapdragon is switched over to use the event
and some hacky U-Boot specific DT overrides (which had to be undone
prior to booting an image) are removed in favour of fixing up the
livetree (which is not passed on to further boot stages).

Finally, some minor fixes are made for the QCM2290 RB1 board, the sdcard
is enabled and it now uses USB host mode in U-Boot like it's bigger
sibling the RB2.

Link: https://lore.kernel.org/r/20250411-livetree-fixup-v2-0-1236823377bb@linaro.org
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Caleb Connolly &lt;caleb.connolly@linaro.org&gt; says:

Introduce a new event to signal that the live tree has been built,
allowing boards to perform fixups on the tree before devices are bound.
Crucially this allows for devices to be enabled or disabled, but also
allows for properties that are parsed during the bind stage to be
modified (such as dr_mode for dwc3).

With this in place, mach-snapdragon is switched over to use the event
and some hacky U-Boot specific DT overrides (which had to be undone
prior to booting an image) are removed in favour of fixing up the
livetree (which is not passed on to further boot stages).

Finally, some minor fixes are made for the QCM2290 RB1 board, the sdcard
is enabled and it now uses USB host mode in U-Boot like it's bigger
sibling the RB2.

Link: https://lore.kernel.org/r/20250411-livetree-fixup-v2-0-1236823377bb@linaro.org
</pre>
</div>
</content>
</entry>
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