u-boot.git/drivers/pinctrl/qcom, branch v2026.01

pinctrl: qcom: add SM7150 pinctrl driver

2025-10-29T11:27:33Z

This SoC features a pinctrl block with north, south, and west tiles accessible to the AP. Signed-off-by: Danila Tikhonov Co-developed-by: Jens Reidel Signed-off-by: Jens Reidel Link: https://lore.kernel.org/r/20250831004602.699953-3-adrian@mainlining.org Signed-off-by: Casey Connolly

drivers: pinctrl: Add Qualcomm SM6350 TLMM driver

2025-10-29T11:27:33Z

Add support for TLMM pin controller block (Top Level Mode Multiplexer) on SM6350 SoC, with support for special pins. Correct pin configuration is required for working debug UART and eMMC/SD cards. Reviewed-by: Neil Armstrong Signed-off-by: Luca Weiss

pinctrl: qcom: sc7280: Fix offset of UFS_RESET

2025-10-29T11:27:33Z

There's no WEST, SOUTH or NORTH in sc7280 pinctrl. Fix the offset of the ufs_reset pin. Fixes: 51ec7fdb64b ("pinctrl: qcom: add sc7280 pinctrl driver") Signed-off-by: Luca Weiss Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20250924-2025-10-misc-v1-1-7e75842ca714@fairphone.com Signed-off-by: Casey Connolly

pinctrl: qcom: add sdm670 pinctrl driver

2025-10-29T11:27:32Z

Add a pinctrl driver for the TLMM block found in the SDM670 SoC. Signed-off-by: David Wronek Link: https://lore.kernel.org/r/20251003-sdm670-v2-3-52c0fa481286@mainlining.org Signed-off-by: Casey Connolly

pinctrl: qcom: sdm845: Limit check off by 1

2025-08-13T13:18:49Z

The driver specifies 154 pins so should have a maximum selector of 153 to ensure that the index into the array special_pins_names does not overflow. This issue was found by Smatch. Signed-off-by: Andrew Goodbody Link: https://lore.kernel.org/r/20250807-pinctrl_qcom-v1-2-42fac6707fd5@linaro.org Signed-off-by: Casey Connolly

pinctrl: qcom: sa8775: Limit check for array index not correct

2025-08-13T13:18:49Z

In sa8775p_get_pin_name the limit check for the index into msm_special_pins_data allows for more elements than exist. Add code to ensure the array index remains in bounds. This issue was found by Smatch. Signed-off-by: Andrew Goodbody Link: https://lore.kernel.org/r/20250807-pinctrl_qcom-v1-1-42fac6707fd5@linaro.org Signed-off-by: Casey Connolly

pinctrl: qcom: Add ipq5424 pinctrl driver

2025-06-23T16:50:21Z

Add pinctrl driver for the TLMM block found in the ipq5424 SoC. Signed-off-by: Varadarajan Narayanan Reviewed-by: Casey Connolly Link: https://lore.kernel.org/r/20250304110105.2762124-6-quic_varada@quicinc.com Signed-off-by: Casey Connolly

Merge patch series "Qualcomm: cleanup OF_LIVE fixup and fix RB1/2"

2025-05-02T14:38:27Z

Caleb Connolly says: Introduce a new event to signal that the live tree has been built, allowing boards to perform fixups on the tree before devices are bound. Crucially this allows for devices to be enabled or disabled, but also allows for properties that are parsed during the bind stage to be modified (such as dr_mode for dwc3). With this in place, mach-snapdragon is switched over to use the event and some hacky U-Boot specific DT overrides (which had to be undone prior to booting an image) are removed in favour of fixing up the livetree (which is not passed on to further boot stages). Finally, some minor fixes are made for the QCM2290 RB1 board, the sdcard is enabled and it now uses USB host mode in U-Boot like it's bigger sibling the RB2. Link: https://lore.kernel.org/r/20250411-livetree-fixup-v2-0-1236823377bb@linaro.org

pinctrl: qcom: qcm2290: fix off by 1 in pin_count

2025-05-02T14:38:03Z

There are 134 pins not 133, oops! This fixes the sdcard on the RB1 as the pins now all get configured correctly. Fixes: 0ecb8cfcb930 ("pinctrl: qcom: add qcm2290 pinctrl driver") Reviewed-by: Sumit Garg Reviewed-by: Neil Armstrong Tested-by: Sumit Garg Signed-off-by: Caleb Connolly

pinctrl: qcom: handle reserved ranges

2025-04-11T13:30:21Z

Some Qualcomm boards feature reserved ranges of pins which are protected by firmware. Attempting to read or write any registers associated with these pins results the board resetting. Add support for parsing these ranges from devicetree and ensure that the pinctrl and GPIO drivers don't try to interact with these pins. Signed-off-by: Neil Armstrong Reviewed-by: Sumit Garg Link: https://lore.kernel.org/r/20250410-topic-sm8x50-pinctrl-reserved-ranges-v2-1-654488392b9a@linaro.org Signed-off-by: Caleb Connolly