u-boot.git/drivers/pinctrl/rockchip, branch v2020.07

common: Drop linux/bitops.h from common header

2020-05-19T01:19:23Z

Move this uncommon header out of the common header. Signed-off-by: Simon Glass

common: Drop log.h from common header

2020-05-19T01:19:18Z

Move this header out of the common header. Signed-off-by: Simon Glass

common: Drop image.h from common header

2020-05-18T21:33:33Z

Move this uncommon header out of the common header. Signed-off-by: Simon Glass

pinctrl: rockchip: Add pinctrl support for rk3308

2019-12-05T16:06:23Z

An iomux register contains 8 pins, each of which is represented by 2 bits, but the register offset is 0x8. For example, GRF_GPIO0A_IOMUX offset is 0x0, but GRF_GPIO0B_IOMUX offset is 0x8, the offset 0x4 is reserved. So add a type IOMUX_8WIDTH_2BIT to calculate offset. Signed-off-by: David Wu Reviewed-by: Kever Yang

pinctrl: rockchip: add px30 pinctrl driver

2019-11-17T09:23:04Z

Add the necessary glue code to allow pinctrl setting on px30 socs. Signed-off-by: David Wu Signed-off-by: Heiko Stuebner Reviewed-by: Kever Yang

pinctrl: rockchip: Also move common set_schmitter func into per Soc file

2019-05-08T09:34:12Z

Only some Soc need Schmitter feature, so move the implementation into their own files. Signed-off-by: David Wu Signed-off-by: Kever Yang

pinctrl: rockchip: Clean the unused type and label

2019-05-08T09:34:12Z

As the mux/pull/drive feature implement at own file, the type and label are not necessary. Signed-off-by: David Wu Signed-off-by: Kever Yang

pinctrl: rockchip: Special treatment for RK3288 gpio0 pins' pull

2019-05-08T09:34:12Z

RK3288 pmu_gpio0 pull setting have no higher 16 writing corresponding bits, need to read before write the register. Signed-off-by: David Wu Signed-off-by: Kever Yang

pinctrl: rockchip: Split the common set_pull() func into per Soc

2019-05-08T09:34:12Z

As the common set_mux func(), implement the feature at the own file for each Soc. Signed-off-by: David Wu Signed-off-by: Kever Yang

pinctrl: rockchip: Special treatment for RK3288 gpio0 pins' drive strength

2019-05-08T09:34:12Z

RK3288 pmu_gpio0 drive strength setting have no higher 16 writing corresponding bits, need to read before write the register. Signed-off-by: David Wu Signed-off-by: Kever Yang